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oddball / ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog
GNU General Public License v2.0
57 stars 19 forks source link

Added a VHDL function to reset a specific register. #29

Closed vermaete closed 3 years ago

vermaete commented 3 years ago

This based on the register address. So, there are now two registers. One to reset all the registers. And one to reset one specific register.

I'm using this function to make a kind of clear-on-write register.

Signed-off-by: Jan Vermaete jan.vermaete@gmail.com

oddball commented 3 years ago

Hi @vermaete !

Sorry didn't see this until now. Despite me trying to fix it, CircleCI does not run the test suit on PRs. I merged your PR to https://github.com/oddball/ipxact2systemverilog/tree/vermaete

The vhdl code generation needs to be fixed.

Screenshot 2021-10-25 at 23 37 22

Can you fix that?

If you want I can give you write access to this repo?! But both SystemVerilog and VHDL generation must work, before we merge into master

vermaete commented 3 years ago

Hi Andreas,

I'll check the VerilogCode and will send you a PR.

Ok for having write access and I will take care of SystemVerilog too. But If you don't mind, I would still do my changes still with a PR?

Top of my list of new things is some generated Python code.

Br,

On Mon, Oct 25, 2021 at 11:47 PM oddball @.***> wrote:

Hi @vermaete https://github.com/vermaete !

Sorry didn't see this until now. Despite me trying to fix it, the circleci does not run the test suit on PRs. I merged your PR to https://github.com/oddball/ipxact2systemverilog/tree/vermaete

The vhdl code generation needs to be fixed.

[image: Screenshot 2021-10-25 at 23 37 22] https://user-images.githubusercontent.com/1045794/138775085-68da537b-51f4-4d57-ab84-b551b20f6627.png

Can you fix that?

If you want I can give you write access to this repo?! But both SystemVerilog and VHDL generation must work, before I merge into master

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub https://github.com/oddball/ipxact2systemverilog/pull/29#issuecomment-951357537, or unsubscribe https://github.com/notifications/unsubscribe-auth/AA5IFKXABWBEWE27XSKDPFTUIXF6HANCNFSM5ERLJG5Q . Triage notifications on the go with GitHub Mobile for iOS https://apps.apple.com/app/apple-store/id1477376905?ct=notification-email&mt=8&pt=524675 or Android https://play.google.com/store/apps/details?id=com.github.android&referrer=utm_campaign%3Dnotification-email%26utm_medium%3Demail%26utm_source%3Dgithub.

-- Jan Vermaete “Success is a self-correcting phenomenom.” -- Gary Hamel

oddball commented 3 years ago

Hi @vermaete !

I managed to get PR's to build from forked repos now, so no need to give you access. (unless you really want)

It looks like its the VHDL code generation that fails. Are you sitting on Mac, Linux or windows? Easy to install GHDL in order to run the tests locally. Although that page has wrong install instructions for mac (brew install ghdl)

vermaete commented 3 years ago

@oddball Please find the fix for the VHDL compilation issue. In the mean time, I have ghdl at Linux/Ubuntu. And Verilator too. Write access could be handy at branches, thanks. All stuff to master I will do with PR to you.

I still have to take o look at your CI/CD. I'm more used to gitlab-ci stuff.