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oddball / ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog
GNU General Public License v2.0
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Reset not mandatory in IP-XACT #3

Closed vermaete closed 10 years ago

vermaete commented 10 years ago

In IP-XACT, the reset element is not mandatory. Added 'reg5' as a copy of 'reg4' but without the 'reset' element.

oddball commented 10 years ago

Hi Vermaete!

This breaks this regression for me. However I suspect a tool bug. Did you do this? make make compile make sim

On Questasim 10.0c_2, in the SystemVerilog code, the reg5 gets a default value of 0. Which I believe is wrong. In the VHDL version, reg5 gets the value x, but it means that the testcase fails for the VHDL version.

I could get around it by not testing the un-reseted registers.

vermaete commented 10 years ago

Hi,

First at all: thanks for this project.

I've using it for a small embedded-C project where I made the documentation in Sphinx/Restructured text. But I will use it for the next HW stuff too.

I could no run the regression from home. I'm missing Modelsim over here. I will try to run it at my clients site. Although it's not the heavy Modelsim stuff over there. Some Microsemi (ex Actel) OEM version and a strong will to go to Isim of Xilinx.

Anyhow: one of the next project will be on Zynq and I thought Xilinx write somewhere not to use asynchronous resets anymore and just synchronous resets if needed.

I'll keep you informed.