Another pull request.
This time it is possible to generated resolved logic (std_logic, std_logic_vector) if selected in the config file.
Default the tool will create unresolved logic. As it was in the past.
When setting 'std' at 'resoved' under vhdl it will generated the more used unresolved logic.
'std' can also be set at 'unresolved'.
[vhdl]
std = resolved
The tests for the no_default test suite are updated. The output of the defaults (being in this case std_ulogic) are still the same.
The code is used and tested in another project without issues.
Would you mind creating another release?
What's still on the list:
generating python code that fits in a UIO driver (by Bruce)
Generating a Wavedrom Bitfield image in the Sphinx documention
Hi Andreas,
Another pull request. This time it is possible to generated resolved logic (std_logic, std_logic_vector) if selected in the config file.
Default the tool will create unresolved logic. As it was in the past. When setting 'std' at 'resoved' under vhdl it will generated the more used unresolved logic. 'std' can also be set at 'unresolved'.
The tests for the no_default test suite are updated. The output of the defaults (being in this case std_ulogic) are still the same. The code is used and tested in another project without issues.
Would you mind creating another release?
What's still on the list:
Br,