Another fix on an issue found by @brucebenedictus,
If an IP block only has read-only registers the compilation of the VHDL code failed.
This commit removes the VHDL code for writable registers in case there are none defined.
I only did this for VHDL. But tested the systemverilog code with the verilator step in the Makefile.
I have no other licenses to test this on verilog.
If this an issue for the merge?
No need yet for a new release. My generation of a document with Wavedrom Bitfield images added and Sphinx is soon ready to be merged.
Hi Andreas,
Another fix on an issue found by @brucebenedictus,
If an IP block only has read-only registers the compilation of the VHDL code failed. This commit removes the VHDL code for writable registers in case there are none defined.
I only did this for VHDL. But tested the systemverilog code with the verilator step in the Makefile. I have no other licenses to test this on verilog. If this an issue for the merge?
No need yet for a new release. My generation of a document with Wavedrom Bitfield images added and Sphinx is soon ready to be merged.
Br