Closed vermaete closed 10 years ago
This does not work. What happens when you have two holes in the register? In SystemVerilog, Hole 1, will be called None, and Hole 2 will be called? Are you running the testcases?
Also I want the SystemVerilog and VHDL structs to have the same fields in the same positions. Common case is to serialize a register over a 1 bit line, and then pack it again on the other side. Perhaps one side is SystemVerilog, and the other VHDL.
Don't know that much about SystemVerilog. And my Modelsim isn't supporting it :-( But I just made (local) a testcase with reg7 with two hole (one more as in the commit). I have added the field 'MSB' at bit 32. Rst (pdf/html) looks fine. VHDL package too.
function reg7_record_type_to_sulv (v : reg7_record_type) return std_ulogic_vector is
variable r : std_ulogic_vector (data_width-1 downto 0);
begin
r := (others => '0');
r(31) := v.field2;
r(25 downto 16) := v.field1;
r(9 downto 0) := v.field0;
return r;
end function;
So, the holes are filled with '0', as it was before the change.
The fields with no name (=None) are not taken in the code to make the RTL or the ReST.
Anyhow, I will check it tomorrow with a better simulator and test it in my design. If I have time, I will make a VHDL testbench.
There is another fix that allows space between two register fields. One that leaves the SystemVerilog generation intact.
Cherry picked: path to export pointing to the xsd files was wrong 99804e5
Closing this PR
I have added a new register (reg7) with a test case.