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ogarnica / TFG2020-21_RISC-V

Proyecto desarrollo chip RISC-V en tecnología STMicroelectronics
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Leer documento flow Cadence #30

Closed ogarnica closed 3 years ago

ogarnica commented 3 years ago

https://www.eng.auburn.edu/~nelson/courses/elec5250_6250/slides/ASIC%20Layout_2%20%20Digital%20Innovus.pdf