AndreaPCalvin
commented
2 years ago El error ya no aparece. Sin embargo, sí que se producen los siguientes warnings:
Warning : Libpin is wider than connected signal. [CDFG-467] : Signal width (10) does not match width of input port 'TA' (11) of instance 'i_mem' of libcell 'ST_SPHD_HIPERF_2048x39m4_Tl' in file '/home/cadence/TFG2020-21_RISC-V/src/eh1/design/lib/mem_lib.sv' on line 239. : This may cause simulation mismatches between the original and synthesized designs. Warning : Libpin is wider than connected signal. [CDFG-467] : Signal width (5) does not match width of input port 'TA' (6) of instance 'i_mem' of libcell 'ST_SPHD_HIPERF_64x21m4_Tl' in file '/home/cadence/TFG2020-21_RISC-V/src/eh1/design/lib/mem_lib.sv' on line 968. Warning : Libpin is wider than connected signal. [CDFG-467] : Signal width (7) does not match width of input port 'TA' (8) of instance 'i_mem' of libcell 'ST_SPHD_HIPERF_256x34m4_Tl' in file '/home/cadence/TFG2020-21_RISC-V/src/eh1/design/lib/mem_lib.sv' on line 598.
Corregido modificando el número de bits de .TA en /home/cadence/TFG2020-21_RISC-V/src/eh1/design/lib/mem_lib.sv
Al ejecutar read_rtl se produce el siguiente error:
Error : Constant expression required. [CDFG-249] [elaborate] : The condition expression in the 'if generate' statement must be constant in file '/home/cadence/TFG2020-21_RISC-V/src/eh1/design/lib/mem_lib.sv' on line 225. : See 'HDL Modeling Guide' for more information. Info : Unable to elaborate the design. [ELAB-4] : Module 'swerv_wrapper' contains errors and cannot be elaborated.
Se trata del if de la memoria de 1024x39