Closed niciki-niciki closed 18 hours ago
Great thank you for your contribution. Can you share a simple Verilog file sample so I can test it after I integrate your mapper?
It works:
Done. I have published Release v1.26.0
Thank you for your contribution
Hi,
Here is my proposal for Verilog mapper.
I made this dedicated mapper to be very simillar to a generic mapper, meaning: . Pattern . Clear . Prefix . Icon
It supports: . Multi-line patterns . DEBUG switch (0/1) to see related regexp in CodeMap list, or not . show_indent switch (0/1) to enable indentiation, or not