Closed GoogleCodeExporter closed 9 years ago
Original comment by olikr...@gmail.com
on 13 Aug 2011 at 9:06
fixed
- clk signal polarity was wrong during init (default level differs vom atmega)
- pin to port mapping are 32/16 bit not 8 bit as on ATMEGA
- timing is critical, processor runs with 80 MHz vs 16 Mhz, so SW SPI has to be
slowed down
Original comment by olikr...@gmail.com
on 20 Aug 2011 at 11:28
Original comment by olikr...@gmail.com
on 20 Aug 2011 at 11:28
Original issue reported on code.google.com by
olikr...@gmail.com
on 13 Aug 2011 at 9:03