Add support for Microsemi Polarfire FPGA

[carlosedp]

Add support for Microsemi Polarfire FPGA

Tracking items:

• [x] Reset button works resetting the heartbeat led so I understand the reset signal gets passed to the core.

This PR depends on Edalize https://github.com/olofk/edalize/pull/212.

[carlosedp]

I might need some help on this one, I added a heartbeat led, it blinks but I see no output on console neither on "q" led.

It synthesizes and PnRs fine tho. Still with 1 core to make tests faster.

[carlosedp]

I believe the problem is having Libero load the memory (.hex) files. I'm seeing the following errors on Synthesize phase:

I tried to load the .hex files directly but got a message saying the file is invalid.

Maybe someone more versed on Libero could chime-in.

[carlosedp]

After a couple exchanged messages with @green4free, Libero expects an Intel-Hex formatted file for memory. Tried loading the generated Hex, I got some errors:

“@E : IHX001 : Intel-Hex record must start with ‘:’ ...”

# After adding : to start of line, I got:

“@E : IHX005 : Intel-Hex record length is invalid”
“@E : IHX004 : Intel-Hex record Byte count is invalid”

According to Magnus, the format is similar to:

Ref: https://en.wikipedia.org/wiki/Intel_HEX

[green4free]

I added the size, address and checksum information for every row for the emitter.hex Libero accepts it as a hex file now, but I have not set up your project, so I can't say that it is read correctly(as in that it is not something completely different that's wring) . :040000004000053780 :040004000010029353 :04000800005500237C :04000C00C00005B774 :040010000015830351 :0400140000237393BF :04001800FE038CE374 :04001C000005C28396 :040020001002E29355 :0400240000129293A1 :04002800005500235C :04002C000012D29359 :0400300000000013B9 :0400340000000013B5 :04003800FE0298E349 :04003C00FD5FF06F05 :040040000013F39323 :04004400FC0396E340 :04004800900005B768 :04004C000005A023E8 :04005000565245536C :040054007375462B4F :04005800436F53653A :04005C00636F72203C :04006000000A736BB4 (I'm not sure how to insert code with line breaks, here) I did it manually now, but it must be some build setting or something that fixes this.

[carlosedp]

I loaded the converted files into the Memory Initialization but it's weird that it inferred 6 instances but only 2 readmemh exists...

It still didn't print anything to serial console...

[carlosedp]

Done, running 882 cores on Polarfire FPGA running in a Polarfire Evaluation Kit board.

[carlosedp]

Added build instructions for Libero configuration on Memory Initialization.

[carlosedp]

I think this is good to go @olofk.

[olofk]

Sorry for taking so long. I just noticed however that there are a ton of reformatting changes to corescore.core. Can we drop those, or are they there for a reason?

Other than that it looks super

[carlosedp]

Ah, I believe my VSCode reformatted it using yaml format. I can drop it if you prefer :)

[olofk]

That would be great. Fine to have it as a separate commit though if it adds consistency

[carlosedp]

Done! I think I'll submit a new PR with reformatting... what do you think? Useful?

[carlosedp]

Another question.. is there a cleaner way to add the post_run to avoid calling python and etc...?

I think I'd change it to: cmd: ["sh", "-c", "cat post-instructions.txt"].

What do you think? Any incompatibility?

[olofk]

It's perfect! Thanks for reminding me about it (again :)).

I guess changing the command to use sh would not work on Windows (what about mac? I guess Libero doesn't run on mac though). Not sure how many Windows users there are out there, and maybe sh exists on windows. I have no idea really. If it's ok on Windows, please change. But I think the python version is pretty clever and you probably already have python3 if you have managed to run FuseSoC and Edalize so it is likely to be available.

[olofk]

And I have no preferences regarding the formatting, so it's fine for me either way

[carlosedp]

That was exactly my thought... it would not work on Windows (works fine on Mac). Since this is run at the end, even with no Libero it works fine giving an output like:

❯ fusesoc run --target=polarfireeval_es corescore
INFO: Preparing ::serv:1.0.2
INFO: Preparing ::verilog-axis:0-r3
INFO: Preparing ::servant:1.0.2
INFO: Preparing ::serving:1.0.2
INFO: Preparing ::corescore:0
INFO: Generating ::corescore-polarfireeval:0
INFO: Setting up project
INFO: Set Libero tool option range to default value IND
INFO: Cores and Libero TCL Scripts generated.

INFO: Executing Libero TCL Scripts.
WARNING: Libero not found on path, execute manually the script "build/corescore_0/polarfireeval_es-libero/corescore_0-run.tcl"
INFO: Running
INFO: Running post_run script libero_post
=========================
Libero build instructions
=========================

After "Generate FPGA Array Data" task, open "Configure Design Initialization Data and Memories" tool.

Click the "Fabric RAMs" tab and select "Initialize all clients from SPI-Flash" in the dropdown named "Initialize all clients from".

Click "Apply".

Select "Design Initialization" tab and set the dropdown "SPI Clock divider value" to "6 (13.33)".

Click Apply

That's fine the way it is :) Thanks for the merge!