Add cmod_a7_35 target.

[bl0x]

This compiles fine with Vivado 2018.2, however when trying to connect with corecount, it does not print anything.

Resource utilisation is as such:

+----------------------------+-------+-------+-----------+-------+
|          Site Type         |  Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs                 | 20287 |     0 |     20800 | 97.53 |
|   LUT as Logic             | 19989 |     0 |     20800 | 96.10 |
|   LUT as Memory            |   298 |     0 |      9600 |  3.10 |
|     LUT as Distributed RAM |    96 |     0 |           |       |
|     LUT as Shift Register  |   202 |     0 |           |       |
| Slice Registers            | 23639 |     0 |     41600 | 56.82 |
|   Register as Flip Flop    | 23639 |     0 |     41600 | 56.82 |
|   Register as Latch        |     0 |     0 |     41600 |  0.00 |
| F7 Muxes                   |   130 |     0 |     16300 |  0.80 |
| F8 Muxes                   |    42 |     0 |      8150 |  0.52 |
+----------------------------+-------+-------+-----------+-------+

[bl0x]

@olofk how would I best investigate this?

[olofk]

Sorry. Completely missed this. First thing to check; does the LED blink? If yes, then it's most likely a UART issue, e.g. wrong baud rate. If not, check for any warnings in the logs (e.g. runme.log in the synth_1 and impl_1 dirs). Check reset polarity (that's a classic). I might be able to run it on my board as well later this week

[bl0x]

There is no LED blinking.

Regarding reset, that one only comes from the clockgen, similar to what is done for arty: o_rst <= !locked_r. The difference being that it is using an MMCME2_ADV instead of the PLLE2_BASE, because of the lower onboard clock freq. I took the code from corescore_marble.v and adjusted the values to produce a 16 MHz clock just like for arty. There is no dedicated reset input.

I'll check the logs and compare to output for arty.

synth: There is one warning about overutilising BRAM (102 out of 100), but then falling back to LUT-RAM (same for arty). Elements wb_en_r_reg, wdata1_r_reg[0] and op26_reg are unused and removed from all cores (same for arty). One warning about MMCME2_ADV not having all required connections (33 out of 7, not in arty log, the same message appears when compiling for marble).

impl: Nothing, really.

[olofk]

Hi @bl0x. I finally found some time to look into this, and I found the issue. It was a classic UART rx/tx swap. The UART pin should be assigned to J18. With that it works totally fine. I can amend it locally and apply if you want

[bl0x]

Hi @olofk , very nice! Thanks for looking into it! And yes, feel free to make the change. I'll have to check it out again =)

[olofk]

Amended and pushed. Thank you for your contributions!

Now I bet you can't fit 101 cores into that chip.... ;)