It would be nice to be able to test a variety of different cores, like VeeRwolf to see how they fit in a given device.
This would allow you to demonstrate the impressive size of SERV by showing how many more copies fit in an FPGA compared to other common RISC-V cores.
It would be nice to be able to test a variety of different cores, like VeeRwolf to see how they fit in a given device. This would allow you to demonstrate the impressive size of SERV by showing how many more copies fit in an FPGA compared to other common RISC-V cores.