search

olofk / edalize

An abstraction library for interfacing EDA tools
BSD 2-Clause "Simplified" License
622 stars 183 forks source link

Support for Intel/Xilinx Power Analysis Tools #115

Open GCHQDeveloper560 opened 4 years ago

GCHQDeveloper560 commented 4 years ago

I've been experimenting with the Quartus (quartus_pow) and Vivado (report_power) power analysis tools and would like to add support to Edalize/FuseSoC

For the most accurate results these tools require post-place and route simulation to generate VCD (Quartus) or SAIF (Vivado) files with information on signal activity. Therefore, I need to add generation of a timing simulation netlist and SDF using quartus_eda or write_verilog/write_sdf. Is this low enough overhead that I should just add it to the existing default flows? If this is an uncommon enough use case that it shouldn't be a default, would adding a netlist option for pnr, a separate option like timing_netlist, or something else make the most sense? Is there a better integration strategy like a post-build hook?

It doesn't appear that Edalize (or IP-XACT) has file types for SDF, SAIF, or VCD, but I don't think Edalize does much with these and it's up to the tool to check file_type.

The next (and longest) step is running the post-place and route simulation. I'm not sure whether this will require any changes for ModelSim or other simulators. The main simulation challenge is the load of plusargs recommended, at least for the Quartus flow, and finding device libraries. This is more of a FuseSoC issue, but it would be nice to be able to chain together targets/tools to be able to do the build, netlisting, simulation, and power analysis with a single command.

Finally, the best way to integrate the power analysis step isn't clear. Would yet another pnr option (power_analysis?) make the most sense?

Thanks for any thoughts!

olofk commented 3 years ago

Apologies for the long wait. As you say, netlist simulation is a pain with the current Edalize structure. I started looking into the next major version of Edalize and summarized some thoughts here. Netlist simulations is a covered use case there. At this point I'm not sure however when I would find time to look at this, so I hope you can (or at this point, preferably already have) come up with a solution that works for you in the meantime.

I think a power_analysis pnr option is fine with the current architecture