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olofk / fusesoc

Package manager and build abstraction tool for FPGA/ASIC development
BSD 2-Clause "Simplified" License
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"fusesoc build" returns zero result code when synthesis fails #118

Closed oleg-nenashev closed 7 years ago

oleg-nenashev commented 8 years ago

Just a follow-up to https://github.com/openrisc/orpsoc-cores/issues/105

When Analysis and synthesis fails for "fusesoc build xxx", fusesoc prints errors to the console, but then exits with the 0 exit code. It may confuse CI, because it requires special handling on it's side.

It happens due to the missing exit() call in https://github.com/olofk/fusesoc/blob/8c1bec7997855a8a3f97e6d1a15464ac6bfb7c23/fusesoc/main.py#L85-L86 . Since the same behavior happens for other commands like pgm, maybe this behavior is "as designed".

Error (10170): Verilog HDL syntax error at orpsoc_top.v(915) near text: ")"; mismatched closing parenthesis . Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /fusesoc/build/sockit/src/sockit/rtl/verilog/orpsoc_top.v Line: 915
Error (10170): Verilog HDL syntax error at orpsoc_top.v(915) near text: ")";  expecting "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /fusesoc/build/sockit/src/sockit/rtl/verilog/orpsoc_top.v Line: 915
Error (10112): Ignored design unit "orpsoc_top" at orpsoc_top.v(36) due to previous errors File: /fusesoc/build/sockit/src/sockit/rtl/verilog/orpsoc_top.v Line: 36
Info (12021): Found 0 design units, including 0 entities, in source file /fusesoc/build/sockit/src/sockit/rtl/verilog/orpsoc_top.v
Info (12021): Found 1 design units, including 1 entities, in source file /fusesoc/build/sockit/src/sockit/rtl/verilog/rom.v
    Info (12023): Found entity 1: rom File: /fusesoc/build/sockit/src/sockit/rtl/verilog/rom.v Line: 36
Info (12021): Found 1 design units, including 1 entities, in source file /fusesoc/build/sockit/src/sockit/rtl/verilog/wb_intercon.v
    Info (12023): Found entity 1: wb_intercon File: /fusesoc/build/sockit/src/sockit/rtl/verilog/wb_intercon.v Line: 1
Info (144001): Generated suppressed messages file /fusesoc/build/sockit/bld-quartus/sockit.map.smsg
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 3 errors, 8 warnings
    Error: Peak virtual memory: 1147 megabytes
    Error: Processing ended: Thu Sep  8 12:29:15 2016
    Error: Elapsed time: 00:00:11
    Error: Total CPU time (on all processors): 00:00:18
Makefile:11: recipe for target 'map' failed
make: *** [map] Error 3
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in elf-loader
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_sdram_ctrl
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_altera_ddr_wrapper
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_intercon
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_intercon-1.0
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in fifo-1.0
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in vlog_tb_utils
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ram_wb
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in stream_utils-1.0
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in elf-loader
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_sdram_ctrl
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_altera_ddr_wrapper
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_intercon
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_intercon-1.0
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in fifo-1.0
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in vlog_tb_utils
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ram_wb
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in stream_utils-1.0
INFO:  Preparing jtag_tap
INFO:  Downloading olofk/jtag from github
INFO:  Preparing verilog-arbiter
INFO:  Downloading bmartini/verilog-arbiter from github
INFO:  Preparing verilog_utils
INFO:  Preparing vlog_tb_utils-1.0
INFO:  Preparing wb_bfm
INFO:  Preparing wb_intercon
INFO:  Preparing wb_common
INFO:  Preparing wb_ram-1.0
INFO:  Preparing wb_avalon_bridge
INFO:  Preparing adv_debug_sys
INFO:  Downloading olofk/adv_debug_sys from github
INFO:  Preparing altera_virtual_jtag
INFO:  Preparing mor1kx
INFO:  Downloading openrisc/mor1kx from github
INFO:  Preparing uart16550-1.5
INFO:  Downloading olofk/uart16550 from github
INFO:  Preparing elf-loader
INFO:  Preparing gpio
INFO:  Preparing vga_lcd
INFO:  Downloading olofk/vga_lcd from github
INFO:  Preparing i2c
INFO:  Downloading olofk/i2c from github
INFO:  Preparing sockit

ERROR: Failed to build FPGA: "make" exited with an error code.
ERROR: See stderr for details.
[Pipeline] sh
[orpsoc-cores] Running shell script
+ mkdir system-sockit
+ mv fusesoc.log system-sockit
[Pipeline] step
Archiving artifacts
[Pipeline] }
[Pipeline] // node
[Pipeline] }
[Pipeline] // parallel
[Pipeline] End of Pipeline
Finished: SUCCESS
oleg-nenashev commented 8 years ago

It happens in http://ec2-52-209-86-82.eu-west-1.compute.amazonaws.com/job/playground/job/orpsoc-cores/10/

imphil commented 7 years ago

PR #146 fixes this

olofk commented 7 years ago

PR #146 is pushed now. Please close if this fixes the issue

imphil commented 7 years ago

@olof that's fixed for sure, you can close it.