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olofk / fusesoc

Package manager and build abstraction tool for FPGA/ASIC development
BSD 2-Clause "Simplified" License
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Use templating engine for generated files #166

Closed imphil closed 6 years ago

imphil commented 7 years ago

Currently we put the templates of the generated project files (e.g. the TCL file for Vivado) inside the backend code itself. That's hard to maintain and annoying to modify.

How about using a templating engine like Jinja for that instead? I'll come up with a patch if you don't have fundamental issues with that @olofk.

In the long run, this would also enable us to let users specify their own template, which is then used and filled by fusesoc. [However, that's optional future stuff, nothing I'm thinking of implementing right now.]

olofk commented 7 years ago

Great! jinja has been suggested before for something else (can't remember what right now). Happy to review such a patch. Also, the makefiles could use that

wallento commented 7 years ago

+1 for jinja

benreynwar commented 7 years ago

Yeah I really like jinja, and have found that the syntax works pretty nicely with both Verilog and VHDL.

On Tue, Aug 22, 2017 at 7:02 AM, Stefan Wallentowitz < notifications@github.com> wrote:

+1 for jinja

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