Closed minjiexm closed 6 years ago
It looks like you are using an older version of the core libraries where i2c did not have a testbench yet. Please run fusesoc update
and see if this solves the issue. Also make sure you are using the latest version of FuseSoC (1.8.1)
hi, olofk:
Thanks and it works.
Please check: ~/Projects/openrisc$ fusesoc sim --sim=icarus i2c WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in fifo-1.0 WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in vlog_tb_utils WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_altera_ddr_wrapper WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in elf-loader WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ram_wb WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in stream_utils-1.0 WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_intercon WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_intercon-1.0 WARN: Warning: Unknown item "name" in section "main" in SD-card-controller-r1 WARN: Warning: Unknown item "default" in section "parameter" in SD-card-controller-r1 WARN: Warning: Unknown item "default" in section "parameter" in SD-card-controller-r1 WARN: Warning: Unknown item "default" in section "parameter" in SD-card-controller-r1 WARN: Warning: Unknown item "default" in section "parameter" in SD-card-controller-r1 WARN: Warning: Unknown item "default" in section "parameter" in SD-card-controller-r1 WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_sdram_ctrl WARN: Unknown section 'rivierapro' in 'mor1kx-generic' INFO: Preparing i2c
../src/i2c/rtl/verilog/i2c_master_bit_ctrl.v:139: Include file timescale.v not found error: Unable to find the root module "orpsoc_tb" in the Verilog source. : Perhaps ``-s orpsoc_tb'' is incorrect? 1 error(s) during elaboration. ERROR: Failed to build simulation model ERROR: Failed to compile Icarus Simulation model