Closed drdavros closed 10 years ago
I am using Xilinx ISE version 14.7 linux
On Sun, Apr 27, 2014 at 3:58 PM, drdavros notifications@github.com wrote:
Hello,
I attempted to build the atlys system using the newer xilinx tools and got an error. Apparently the method used to divide the clock in dvi_gen_top.v is now illegal.
From Xilinx: In Spartan-6 FPGA, the BUFIO2 using the DIVIDE(2) applications can occasionally enter a stuck state. Hence, it is not supported and an alternative implementation needs to be used.
The error from Xilinx ISE when building the atlys system: ERROR:PhysDesignRules:2502 - Issue with pin connections and/or configuration on block::. BUFIO2 has an invalid setting of DIVIDE by 2. This setting is not supported. For more information please see Answer Record 56113.
Ok, thanks for the report. I'll take a look at it, but if you come up with a solution yourself before I do, please keep us posted. Btw, this issue-report would probably have been more suited for openrisc/orpsoc-cores.
Stefan
Closing this now
Hello,
I attempted to build the atlys system using the newer xilinx tools and got an error. Apparently the method used to divide the clock in dvi_gen_top.v is now illegal.
From Xilinx: In Spartan-6 FPGA, the BUFIO2 using the DIVIDE(2) applications can occasionally enter a stuck state. Hence, it is not supported and an alternative implementation needs to be used.
The error from Xilinx ISE when building the atlys system: ERROR:PhysDesignRules:2502 - Issue with pin connections and/or configuration on block:<dvi_gen0/sysclk_div>:. BUFIO2 has an invalid setting
of DIVIDE by 2. This setting is not supported. For more information please
see Answer Record 56113.
Thanks,