olofk / fusesoc

Package manager and build abstraction tool for FPGA/ASIC development
BSD 2-Clause "Simplified" License
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Prepending generated core files #636

Closed garankonic closed 10 months ago

garankonic commented 1 year ago

This merge request allows to prepend generated core files right before the core that instantiates a generator.

Use-case: ModelSim requires vhdl files to be built in the right order. Imagine you generate a vhdl file (e.g. package with settings) and you want to use it already in the parent core. Using "first" position does not work if the package itself depends on some other package (core). Here is the example dependency tree, to make things clear: common_core <- generated_core (depends on common_core) <- current_core (has common_core in dependencies, instantiates generator to produce generated_core). If using "first" keyword, it would appear in the following order "generated_core <- common_core <- current_core" - which will not work.

olofk commented 1 year ago

Excellent! Thanks for fixing this. It doesn't pass the syntax check however. Here are some quick notes on how to enable the automatic syntax checks when you commit code.

Bonus points if you can come up with a testcase for this as well so that we don't accidentally break it in the future

garankonic commented 1 year ago

Hey. Sorry for reacting so late, I thought adding tests would take more time:) Now should work fine (apart from the readthedocs - seems that your latest commit to the main affected this job somehow) Cheers

olofk commented 10 months ago

Excellent. Looks perfectly fine now. Thank you for your contribution. Picked and pushed!