olofk / fusesoc

Package manager and build abstraction tool for FPGA/ASIC development
BSD 2-Clause "Simplified" License
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Add syntax to map parameter to a specific toplevel #667

Open olofk opened 5 months ago

olofk commented 5 months ago

When using multiple top levels, which sometimes is the case for simulations, there is currently no way to tell the EDA tools which toplevel that should use a specific parameter. Unfortunately, it seems like some EDA tools get angry when they receive parameters that they don't know about.

One idea could be to have an optional dot notation for the parameters key in the target section, e.g.

targets:
  sim:
    ...
    parameters: [some_param, specific_top.another_param]

which would send some_param to all toplevels but only send another_param to the specific_top toplevel