Fusesoc yosys target creates fusesoc error and a partially complete Makefile

Fusesoc file:

CAPI=2:

name: core_rtl:common:sync_fifo_1c_rw:1.0.0
description: common rtl IP for synchronous Fifo, 1 clock and RW

filesets:
  fs_rtl:
    files:
      - vlog/sync_fifo_1c_rw.sv
    file_type: systemVerilogSource
  fs_syn_yosys:
    files:
      - yosys.tcl: {file_type: tclSource, copyto: .}
targets:
  default: &default
    description: Define RTL fileset and default tool
    filesets:
      - fs_rtl
    toplevel: ["is_toplevel? (sync_fifo_1c_rw)"]
    default_tool: icarus
  yosys_syn
    description: synthesize with Yosys
    default_tool: yosys
    filesets: [fs_rtl, fs_syn_yosys]
    tools:  yosys_syn:
      yosys:
        arch: ice40
        output_format: verilog
        yosys_template: [yosys.tcl]
    toplevel: sync_fifo_1c_rw

Fusesoc command:

fusesoc --cores-root=.. run --run --target yosys_syn core_rtl:common:sync_fifo_1c_rw:1.0.0

Fusesoc error when you run it once:

INFO: Preparing core_rtl:common:sync_fifo_1c_rw:1.0.0
INFO: Setting up project
Traceback (most recent call last):
  File "/home/berver007/work/tools/oss-cad-suite/bin/fusesoc", line 8, in <module>
    sys.exit(main())
             ^^^^^^
  File "/home/berver007/work/tools/oss-cad-suite/lib/python3.11/site-packages/fusesoc/main.py", line 672, in main
    fusesoc(args)
  File "/home/berver007/work/tools/oss-cad-suite/lib/python3.11/site-packages/fusesoc/main.py", line 662, in fusesoc
    args.func(fs, args)
  File "/home/berver007/work/tools/oss-cad-suite/lib/python3.11/site-packages/fusesoc/main.py", line 332, in run
    backend.configure()
  File "/home/berver007/work/tools/oss-cad-suite/lib/python3.11/site-packages/edalize/edatool.py", line 231, in configure
    self.configure_main()
  File "/home/berver007/work/tools/oss-cad-suite/lib/python3.11/site-packages/edalize/yosys.py", line 159, in configure_main
    commands.write(os.path.join(self.work_root, "Makefile"))
  File "/home/berver007/work/tools/oss-cad-suite/lib/python3.11/site-packages/edalize/utils.py", line 55, in write
    f.write(" " + d)
            ~~~~^~~
TypeError: can only concatenate str (not "list") to str

Note: this creates a Makefile even though it errors out:

#Auto generated by Edalize

all: core_rtl_common_sync_fifo_1c_rw_1.0.0.verilog

core_rtl_common_sync_fifo_1c_rw_1.0.0.verilog:

Make would not do anything because the command is missing.

Interestingly, not removing the build dir, rerunning the same fusesoc command yields:

INFO: Preparing core_rtl:common:sync_fifo_1c_rw:1.0.0
INFO: Running

The error disappears, I assume because the Makefile exists and is not regenerated.

GOAL

The goal of this exercise was to get yosys and the yosys template working for asic node(s) that are not necessarily the open source PDKs. And to make sure I have control over all the tools that are used. Both requirements do exclude the use of an all-in one flow like OpenLane. Hence, my trial and error. The first step is obviously to find information on the yosys tool and the options supported by edalize. Unfortunately read the docs was not my friend nor was Google. So, I started experimenting and I might have done something what I wasn't supposed to do (have a fileset with yosys.tcl and specifiy it as well as yosys_template. Still peculiar that it first fails and then successfully runs.

olofk / fusesoc

Fusesoc yosys target creates fusesoc error and a partially complete Makefile #692