Closed salmansheikh closed 6 years ago
This would require a new backend module for Libero similar to the ISE and Quartus files here https://github.com/olofk/fusesoc/tree/master/fusesoc/build
But what cores need to be custom for the ProASIC? I think there are subtle nuances between xilinx and altera beyond just the tools called and pins, right? Or are all the cores the same exactly?
That's hard to tell, but hopefully, we just need a new top-level core. We used to build against a ProASIC3 in orpsocv2, and I don't think we did anything special for the cores we used there
Closing due to inactivity
What changes needed to use this for an Actel ProASIC3? Which modules need customization?