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olofk / serv

SERV - The SErial RISC-V CPU
ISC License
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Make serv_alu.v synthesizable with Vivado #108

Closed pqcfox closed 9 months ago

pqcfox commented 10 months ago

Currently, serv_alu.v uses the one-bit unsized literal '0 which Vivado doesn't support unless a .sv file extension is used.

To recreate the error, run fusesoc run --tool=vivado serv --pnr=none --part=xc7a100tcsg324-1. Synthesis should terminate with an error.

This change resolves the Xilinx synthesis error.

pqcfox commented 10 months ago

Anything I should do to fix the Read the Docs workflow build failure, or is that expected for now?

olofk commented 9 months ago

Hmm... this is strange. I thought I had fixed the readthedocs failure already. Will need to take another look. Anyway, your patch looks totally fine. Thank you for your contribution. Picked and pushed!