Closed monstrous-moonshine closed 9 months ago
Good catch. I have been running with an older version of Verilator that didn't catch this issue. It turns out that the CI also runs an older verilator which is why it wasn't discovered there either. Anyway, thanks for reporting. I'll fix.
Ok, I pushed a fix for this now. Please let me know if that helps
Yes, works like a charm. Thanks for the fix!
Running the following command produces lint errors from Verilator:
``` INFO: Preparing ::serv:1.2.1 INFO: Setting up project INFO: Building simulation model INFO: verilator -f serv_1.2.1.vc -Wall ERROR: %Warning-GENUNNAMED: src/serv_1.2.1/rtl/serv_rf_ram_if.v:65:29: Unnamed generate block 'genblk1' (IEEE 1800-2017 27.6) : ... Suggest assign a label with 'begin : gen_$ fusesoc run --target=lint serv
These are the versions of SERV, Verilator, and FuseSoC:
I followed the steps outlined in the README:
I think these might be relevant to the error:
I'm opening this issue because I think the author(s) intend the RTL to pass the linter, so I wanted to know if I'm missing anything obvious. Any help would be appreciated.