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olofk / serv

SERV - The SErial RISC-V CPU
ISC License
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Declare variables/nets before referenced #62

Closed hakan-demirli closed 2 years ago

hakan-demirli commented 2 years ago

Modelsim tends to get quite angry when it sees a variable that is not declared.

serv_decode.v: "op_or_opimm" serv_immdec.v: "signbit" serv_top.v: "dbus_rdt" Can we move them before they are referenced?

This has happened after https://github.com/olofk/serv/commit/6e802cb9bc19cefeae5d7e60d75bd6b9edb7230a

zeeshanrafique23 commented 2 years ago

Hmm, thanks for letting us know. I am amazed that Verilator doesn't catch this.

olofk commented 2 years ago

Thanks for reporting. Yes, this should be fixed

@zeeshanrafique23 the problem is that this is totally valid to do in Verilog but ModelSim (and a few more tools) don't accept it. I have fixed this issue in SERV (and many other projects) before but it's easy to miss when code gets rewritten

zeeshanrafique23 commented 2 years ago

Ah my bad, I wasn't aware of this thing before. There is one more signal dbus_ack in serv_top.v that should also be declared before it referenced, same as dbus_rdt.

zeeshanrafique23 commented 2 years ago

@olofk Just made corrections, let me know if further changes are needed.

zeeshanrafique23 commented 2 years ago

@hakan-demirli this is resolved. Thanks for letting us know.