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olofk / serv

SERV - The SErial RISC-V CPU
ISC License
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Guarantee at least 2 cycles of o_rst after PLL locked. #89

Closed emeb closed 2 years ago

emeb commented 2 years ago

While helping someone to bring up FuseSOC Serv on a new platform we were having trouble starting up after configuration. Digging into the clock and reset generation I discovered that the wb_rst signal generated in the ice40_pll.v module was not asserting during start up.

The circuit relies on the PLL lock signal to clear the reset after two clock cycles, but because the initial state of the two delay registers defaults to logic 0, the reset signal is not guaranteed to ever assert.

Adding an "initial" block to start those registers out at logic 1 ensures that at least two cycles of reset are generated after the device comes out of configuration and then we were able to see the Serv CPU starting up.

emeb commented 2 years ago

I have no idea why the Linter CI check failed - I haven't touched the script and it appears to not be an issue with my code but rather with the scripting.