olofk serv issues - Githubissues

olofk / serv

SERV - The SErial RISC-V CPU

ISC License

1.43k stars 188 forks source link

issues

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Allow mpie bit to be writeable in mstatus

#31 btashton opened 4 years ago
5
RISCV Compliance fails

#30 ion-concepts closed 4 years ago
4
Update alhambra board

#29 imuguruza closed 4 years ago
1
Add Saanlima pipistrello spartan6 LX45

#28 trabucayre closed 4 years ago
1
Add compatibility with Xilinx ISE

#27 trabucayre closed 4 years ago
1
Using wb_intercon for servant

#26 tcmichals closed 2 years ago
2
Add Saanlima pipistrello spartan6 LX45 with note for WA due to ISE bugs

#25 trabucayre closed 4 years ago
5
Yosys error: Signal `\o_par' with invalid width range -1

#24 gregdavill closed 4 years ago
3
Add Alhambra board to repo

#23 imuguruza closed 4 years ago
0
Zephyr hello world in Alhambra board

#22 imuguruza closed 4 years ago
10
Example code for "8 RISC-V cores and a USB core"?

#21 nalzok closed 2 years ago
5
Various command line options not working: --firmware, --uart_baudrate

#20 tomverbeure closed 4 years ago
3
Error: Specified --top-module 'servant_sim' was not found in design.

#19 ekiwi closed 4 years ago
4
Declare variables/nets before referenced

#18 dh73 closed 4 years ago
1
addi opcode wrong result

#17 MaximMndv closed 3 years ago
11
Add Arty a7 35t support

#16 trabucayre closed 4 years ago
1
README: argument to use blinky example instead of hello world is true for all boards

#15 trabucayre closed 4 years ago
1
README: --firmware parameter only available for sim and verilator_tb targets

#14 trabucayre closed 4 years ago
1
Run on hardware error

#13 Martoni closed 4 years ago
4
path correction and little comment

#12 Martoni closed 4 years ago
3
Stuck in loading RAM

#11 Martoni closed 5 years ago
15
Suppressing some verilator lint warnings

#10 Martoni closed 5 years ago
1
Update README.md

#9 Martoni closed 5 years ago
2
Add a step for yosysSynthesisReport() to Jenkinsfile

#8 Nancy-Chauhan closed 2 years ago
1
rtl: Improve compatibility with Synopsys Design Compiler

#7 zarubaf closed 5 years ago
1
Yosys Synthesis error : ImportError

#6 Nancy-Chauhan closed 5 years ago
4
Yosys assertion error on shift_reg

#5 nturley closed 5 years ago
4
Update serv_top.v

#4 AlAlves closed 5 years ago
1
added Logo ;)

#3 drom closed 5 years ago
0
background info

#2 maidenone closed 2 years ago
9
trying to follow the Prerequisites instructions

#1 maidenone closed 2 years ago
6