Odin inserts undriven signals in netlist

ominux / vtr-verilog-to-routing

Automatically exported from code.google.com/p/vtr-verilog-to-routing

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For the following example, Odin inserts undriven signals (named  
top^BUF_NODE~...) in a netlist.  This appears to have something to do with the 
black box instantiation.

Here is the source Verilog:

  module test (a, x, y);
  input  a;
  output x;
  output y;

  wire t1;
  wire t2;

  split split_a (.a(a), .x(t1), .y(t2));  // Blackbox specified in arch file.

  assign x = t1;
  assign y = t2;

  endmodule

And here is the BLIF that Oden generates:

  .model test
  .inputs top^a
  .outputs top^x top^y

  .names gnd
  .names unconn
  .names vcc
  1

  .names top^BUF_NODE~1 top^x
  1 1

  .names top^BUF_NODE~2 top^y
  1 1

  .end

  .model split
  .inputs a
  .outputs y x
  .blackbox
  .end

Note that top^BUF_NODE~1/2 signals are not defined.

Any help to resolve this bug would be greatly appreciated.  This is currently 
holding up our project.

Thanks!

-Tom

Original issue reported on code.google.com by tomahawkins on 11 Mar 2015 at 12:23

It looks like your hardware primitive "split" is not being instantiated. Can you attach your architecture file that contains the hardware primitive "split" so that we can see why this is happening? Ken, I think we should error out in Odin II when a user defines a blackbox that we cannot instantiate. I hypothesize that Odin II recognized that "split" is a black box but couldn't find "split" in the architecture file so ignored instantiating it.

ominux / vtr-verilog-to-routing

Odin inserts undriven signals in netlist #103