ominux / vtr-verilog-to-routing

Automatically exported from code.google.com/p/vtr-verilog-to-routing
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Bad annealing selection code fixed #37

Closed GoogleCodeExporter closed 9 years ago

GoogleCodeExporter commented 9 years ago
What steps will reproduce the problem?
1. Compile any circuit
2.
3.

What is the expected output? What do you see instead?

Observe that empty blocks all appear on the top row.  If the circuit has 
multipliers/memories, then those get pushed to the bottom.

This was a scary bug in VPR 5.0 lasting to just last week.  The find_to 
function in place.c had a natural bias down 1.  In fact, when rlim == 1, it 
always returns Y - 1 from the "from" position.  This has huge consequences on 
QoR for cases where the circuit has fixed I/O pins and has any degree of 
sparsity (ie. real FPGAs).  

Fortunately, from reviewing our loads of regression tests, this bug generally 
did not empirically affect QoR in prior experimental results for two reasons:
1. We always let the FPGA resize so for a densely packed FPGA, the from 
function still allows blocks to get swapped from the top positions
2. Since I/Os are free floating in almost all academic research, blocks that 
gravitate to the bottom that are connected to I/Os will naturally drag the I/Os 
down to the bottom.

The re-done find_to function I put in is slower than the original but it is 
correct and a lot more generic.  The assumptions that I/Os are at the perimeter 
as well as all columns in the core must contain the same block type have been 
removed.

Original issue reported on code.google.com by JasonKai...@gmail.com on 4 Aug 2012 at 2:35