LUT size 2 has problems

[GoogleCodeExporter]

What steps will reproduce the problem?
1. change the original architecture file with the release to support LUT size 2
2. the changed file is attached

Output:
3. abc reports errors "Incorrect LUT SIZE (2)"
4. we have changed the file to support lut size 3-7, and they are working.

Original issue reported on code.google.com by qiang.li...@gmail.com on 12 Nov 2012 at 2:15

Attachments:

• k2_N1_soft_logic_only.xml

[GoogleCodeExporter]

ABC does not support tech mapping to 2-LUTs.  If you need 2-LUTs, then you'll 
have to modify ABC to handle it.  Or alternatively, you can talk with the 
developers of ABC to see if they have a version that supports 2-LUTs.

Original comment by JasonKai...@gmail.com on 12 Nov 2012 at 7:43

• Changed state: WontFix

[GoogleCodeExporter]

Dear helper,

Thanks for the answer.

Another question:

When I increase LUT size from 3 to 7, the total logic area reported by the
VTR in vpr.out gets decreased. Previous works such as "VPR 5.0: FPGA CAD
and architecture exploration tools..." reported the reverse trend. I found
that the issue may be caused by the grid_logic_tile_area setting. For
different LUT sizes, should this parameter take different values? If so,
how can we calculate it? If not, then how to calculate the total logic area
so that I can observe the similar results as the mentioned reference paper?
Certainly, increasing LUT size reduces the layout grid size.

many thanks.
Qiang

Original comment by qiang.li...@gmail.com on 16 Nov 2012 at 2:25

[GoogleCodeExporter]

Hello Qiang,

Yes, you need to increase the grid_logic_tile_area to correspond with the 
increase in area of your CLBs when you sweep different LUT sizes.  This is 
actually a difficult number to obtain from scratch (ie. you need to use SPICE 
to optimize the size of the transistors of your CLB then measure the total area 
consumed).  For this reason, to make it easier for researchers to explore 
different architectures, we have included several transistor optimized 
architecture files here: 
http://www.eecg.utoronto.ca/vpr/architectures/architecture_table.html

Note: These architecture files are VPR 5.0 architecture files so you need to 
manually convert them over to VPR 6.0.

Original comment by JasonKai...@gmail.com on 16 Nov 2012 at 5:17

[GoogleCodeExporter]

Hello,

Many thanks for the quick reply. I had a quick look at the table and the
files. Another two questions:

1. Is the grid_logic_tile_area different for different combination of K, N,
L, Fc_in and Fc_out? What is the unit?
2. The value of grid_logic_tile_area in each arch file is different from
the Tile Area in the table for each arch. What is the difference?

Thanks.
Qiang

Original comment by qiang.li...@gmail.com on 16 Nov 2012 at 6:36

[GoogleCodeExporter]

1.  grid_logic_tile_area is only for area within a logic block (ie. CLB).  So 
you should change it for every K and N combination.   It is in minimum width 
transistor units (MWTU).

2.  Tile Area in the table is the logic + routing tile area in um^2.

Original comment by JasonKai...@gmail.com on 16 Nov 2012 at 3:11

[GoogleCodeExporter]

you should change it for every K and N combination.   It is in minimum
width transistor units (MWTU).

1. Do you have any suggestion, If we want to try different combination of K
(3-7) and N (2, 4, 6, 8)? The table you sent just includes N=4, 10. Could
you kindly provide grid_logic_tile_area values for the combinations?

2. grid_logic_tile_area is also different for different L values. For
example, N04K04L01.FC15FO25.AREA1DELAY1.CMOS130NM.BPTM and
N04K04L02.FC15FO25.AREA1DELAY1.CMOS130NM.BPTM have
different grid_logic_tile_area values.

Thanks a lot.
Qiang

Original comment by qiang.li...@gmail.com on 19 Nov 2012 at 1:57