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ominux / vtr-verilog-to-routing

Automatically exported from code.google.com/p/vtr-verilog-to-routing
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VPR Placement has a bias down to the bottom #51

Closed GoogleCodeExporter closed 9 years ago

GoogleCodeExporter commented 9 years ago 
Symptom:
   The problem happens with many benchmarks.
It is more visible when given a fixed number of tracks with lower utilization.
One can see that close to the end of placement, the placed design always
consolidates (or sinks) to the bottom of the arrays, even the IO pads are 
locked to the top.

To reproduce the problem, 
1. Take a benchmark, for example, sha.
2. Specify a larger array size to make the utilization, say, around 30%.
3. Lock the pins to the top (optional).
Then run VPR placement. One can see that it always sinks to the
bottom at the end of placement.  

Possible Solution:
   I think the issue comes from vpr/SRC/place/place.c function "find_to()"
and line "y_rel = my_irand(max (0, ((max_y - min_y) / type->height) - 1));".
The "-1" causes the drifting down and should be removed.
Please take a look and verify it. 

Thanks.
Jianshe
Efinix Inc.

Original issue reported on code.google.com by Jas...@efinixinc.com on 16 Nov 2012 at 9:01

GoogleCodeExporter commented 9 years ago 
This issue has already been fixed in the trunk.  You can get it in the next 
release or download the trunk code and use it now.

Original comment by JasonKai...@gmail.com on 16 Nov 2012 at 10:18