Closed GoogleCodeExporter closed 9 years ago
Hi Tim,
The arch file doesn't load. When I run vpr, I get the following:
ERROR(1): [LINE2978] Duplicate interconnect name: 'control_2' in mode: 'alm'
Original comment by JasonKai...@gmail.com
on 7 Jun 2013 at 8:15
Original comment by JasonKai...@gmail.com
on 7 Jun 2013 at 8:16
Problem in bad arch loading found to be errors in the arch file interconnect
specification that didn't get flagged in previous versions of VPR. A working
architecture file is attached.
Problem reproduced with new arch file.
Original comment by JasonKai...@gmail.com
on 7 Jun 2013 at 8:41
Attachments:
Critical error in multi-clock timing analyzer. Multi-clock timing analyzer had
explicit check that ignores all non-ff netlist sinks. This means that the
timing of blocks such as memories did not work. This bug only affects VPR 7
because it comes about from multi-clock analysis. The VPR 6 release timing
analysis results are fine because it assumes single clock analysis.
Original comment by JasonKai...@gmail.com
on 11 Jun 2013 at 1:14
Attached the working test.xml arch file
Original comment by JasonKai...@gmail.com
on 18 Jun 2013 at 4:49
Attachments:
Original issue reported on code.google.com by
violale...@gmail.com
on 7 Jun 2013 at 7:47Attachments: