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ominux / vtr-verilog-to-routing

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Stratix4 Arch with Timing failed assertion when reading in blif #64

Open GoogleCodeExporter opened 9 years ago

GoogleCodeExporter commented 9 years ago 
What steps will reproduce the problem?
1.Issue can be reproduced with command: vpr pretty_clk.xml 
sudoku_check_stratixiv_arch_simple -pack -place -nodisp -timing_analysis on
2.Failed assertion test at line 715 in read_blif.c: 
assert(logical_block[num_logical_blocks-1].clock_net == OPEN);

Seems like a clock related issue but I couldn't figure out the exact cause.

Tim

Original issue reported on code.google.com by violale...@gmail.com on 3 Jul 2013 at 4:26

Attachments:

GoogleCodeExporter commented 9 years ago 
arch file

Original comment by violale...@gmail.com on 3 Jul 2013 at 4:29

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GoogleCodeExporter commented 9 years ago 
A little more detail:
- Tim tells me this is a RAM block.
- There are two clock pins marked on the RAM block.  Is this supported in VPR 
at this point?
- This error is important because it is gating progress on making the Titan 
benchmark set timing-driven.

Vaughn

Original comment by vaughnb...@gmail.com on 3 Jul 2013 at 5:28