i am usin vtr version 6 as cad tools so i wrote a simple verilog code as
included in the attached file but ODIN II is faild to synthesis, so it would be
appricated if some body can help me to fix this problem
regards
Abdullah
Original issue reported on code.google.com by abdullah...@googlemail.com on 27 May 2014 at 1:09
Original issue reported on code.google.com by
abdullah...@googlemail.com
on 27 May 2014 at 1:09Attachments: