What steps will reproduce the problem?
1. ./odin_II.exe -V top_UART.v -a sample_arch.xml
2. Run in Icarus Verilog and the verilog file compiles and runs
3.
What is the expected output? What do you see instead?
Synthesized blif file , ready for optimization using abc
What version of the product are you using? On what operating system?
Ubuntu, VTR Version 7.0 Full Release
Please provide any additional information below.
Original issue reported on code.google.com by david.dh...@gmail.com on 11 Jul 2014 at 7:02
Original issue reported on code.google.com by
david.dh...@gmail.com
on 11 Jul 2014 at 7:02Attachments: