spree.v doesn't go through Odin

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What steps will reproduce the problem?
1. Run benchmarks/verilog/spree.v with the basic flow architecture

What is the expected output? What do you see instead?
The flow says that Odin failed, and odin.out does not provide any details
(not even "you have failed").

What version of the product are you using? On what operating system?
VTR 7.0 on Ubuntu 12.04.4 LTS

Original issue reported on code.google.com by edin.kad...@gmail.com on 22 Aug 2014 at 1:44

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This is an update on this issue, I was able to resolve it by modifying spree.v 
in the ways described below. Note that running spree.v directly with Odin gives 
a segfault.

There are two problems with spree.v:

1) The memories have depth 2**32, which is too big for Odin. Normally it would 
complain when depth>2**25, but here it doesn't because one of the memories has 
a different bitwidth for the addresses of the two ports, so I guess it gets 
confused.
The fix is to reduce the bitwidth (down to 13/14 bits seemed to make sense 
given the code and comments around). Note that each one of the 4 memories has 
this problem.

2) Modules pipereg_w5 and pipereg_w6 cause a segfault as well.
Even though the other pipereg_wX modules are very similar, they don't cause 
faults, and it seems that the problem is when the bitwidth of the output 
register is 32bits.
My fix was to keep the output as q, call the register r, replace q with r 
inside the assign statement, and write "assign q = r;".

Attached is a modified version of spree.v that goes through Odin. Each line 
I've changed has the comment "//segfault fix".

Original comment by edin.kad...@gmail.com on 28 Oct 2014 at 9:30

Attachments:

• spree.v

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Actually, for the two reg file memories, I guess it makes more sense to give 
the addresses a bitwidth of 5 (depth of 32, or 32 registers for the processor).

Original comment by edin.kad...@gmail.com on 28 Oct 2014 at 9:44