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onchipuis / mriscvcore

A 32-bit RISC-V processor for mriscv project
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Timeout in simulation #2

Closed olofk closed 7 years ago

olofk commented 7 years ago

I'm working on packaging mriscv for FuseSoC, but I haven't been able to complete any simulations yet. Running with the default firmware I just get lines saying 7..OK over and over again until the simulations times out

olofk commented 7 years ago

That comment was for the mriscvcore_tb, but actually, I can't get any of the testbenches working. sim_IRQf (in IRQ_tb) doesn't do anything, MULT_tb doesn't work because funct3 isn't defined on the UUT and both sim1 (in ALU_tb) and Sim_DecInstru1 (in DECO_INSTR_tb.v) also tries to use ports that doesn't exist on the UUT

onchipuis commented 7 years ago

Fixed in https://github.com/onchipuis/mriscvcore/commit/6ac262b776bf23ceadd42651092a762891b7fdfa Added an "OK" detector. About the other testbenches, they will be corrected because they were used for the previous implementations of each block. But we use the RISC-V tests for testing each implemented instruction. Thanks for reporting.