FPGA: Add task_sequence_parallel_loop Tutorial

[chanjunc-intel]

Adding a New Sample(s)

Description

This sample is an FPGA tutorial that demonstrates how to use task sequences to achieve asynchronous parallelism within kernel. This task sequences implementation uses inter-kernel pipes to pass data between loops and applies task sequences to schedule loops to run concurrently. The naive implementation uses arrays to pass data between loops and each loop are scheduled to run sequentially.

Checklist

Administrative

• [X] Review sample design with the appropriate Domain Expert: <Yohann Uguen @yuguen-intel>
• [ ] If you have any new dependencies/binaries, inform the oneAPI Code Samples Project Manager

Code Development

• [X] Implement coding guidelines and ensure code quality. see wiki for details
• [X] Adhere to readme template
• [X] Enforce format via clang-format config file
• [X] Adhere to sample.json specification. https://github.com/oneapi-src/oneAPI-samples/wiki/sample-json-specification
• [ ] Ensure/create CI test configurations for sample (ciTests field) https://github.com/oneapi-src/oneAPI-samples/wiki/sample-json-ci-test-object
• [X] Run jsonlint on sample.json to verify json syntax. www.jsonlint.com
• FPGA regtest(s): Windows: naive: https://spetc.intel.com/testsummary?testRunIds=10057262 optimized: https://spetc.intel.com/testsummary?testRunIds=10066030 FPGA regtest(s): Linux: naive: https://spetc.intel.com/testsummary?testRunIds=10057447 optimized: https://spetc.intel.com/testsummary?testRunIds=10066029

Security and Legal

• [ ] OSPDT Approval (see Project Manager for assistance)
• [ ] Compile using the following compiler flags and fix any warnings, the falgs are: "/Wall -Wformat-security -Werror=format-security"
• [ ] Bandit Scans (Python only)
• [ ] Virus scan

Review

• [ ] Review DPC++ code with Paul Peterseon. (GitHub User: pmpeter1)
• [ ] Review readme with Tom Lenth(@tomlenth) and/or Project Manager
• [ ] Tested using Dev Cloud when applicable

[yuguen-intel]

Waiting for @whitepau approval