The PML analyzer is an open source API providing a simple DSL to build a description of the architecture of your chip based on the PHYLOG Modelling Language (PML).
The estimation of non exclusive scenarios is way to slow (several minutes for Keystone).
Either provide an option to bypass it since it is only providing additional infos or provide a more efficient implementation.
The estimation of non exclusive scenarios is way to slow (several minutes for Keystone). Either provide an option to bypass it since it is only providing additional infos or provide a more efficient implementation.