Open robben225 opened 9 months ago
Same question here, wondering if that is due to the lack of support for vector extension of x86 cpu
Sorry, we have not implemented the SIMD code generation for CONV in onnx-mlir, in part because our accelerator handles it very well.
If you are interested in contributing a CPU SIMD implementation, I started doing a layout optimization to change a NCHW to a layout that split C into an outer C and an inner C (NxC1xHxWxC2) where C2 is sized to be SIMD friendly. I paper by Jiyuan Zhang et al entitled "High Performance Zero-Memory Overhead Direct Convolutions" is a refinement where H and W are also tiled.
I can help with the layout transformation if you are willing to write the accelerated CONV also.
Hi Thanks for replying! I was planning on codegen/C API calls for further lowering from krnl to llvm level. I will be checking more on this. Thanks!
I find the “simd-data-layout” option in the help “onnx-mlir” command,it says “Enable SIMD optimization for convolution (default=false). Set to 'true' if you want to enable SIMD optimizations.” But when I execute the following command to compile mobilenetv2: “onnx-mlir mobilenetv2.onnx --simd-data-layout”, an error is printed:“loc("Conv_4"): error: failed to legalize operation 'onnx.Conv' that was explicitly marked illegal”. Does anyone know what the reason is?