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open-ephys / next-gen-system

work in progress repository for next generation acquisition and closed-loop feedback system
https://open-ephys.atlassian.net/wiki/display/OEW/PCIe+acquisition+board
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TODO before first fab run #1

Closed jonnew closed 8 years ago

jonnew commented 8 years ago
  1. Double check FMC pinout and make sure we are not doing something stupid, like tying one of the many ground pins to power or something
  2. Trace each LVDS signal to each omnetics connector: Polarities right?
  3. Double check pinouts for all ICs
  4. Decoupling caps need to be moved as close a possible to respective ICs. Get rid of power and ground traces wherever possible -- these should dive right into the correct plane.
  5. Make sure high speed lines (1) don't have stubs and (2) stay close if they are differential
  6. Look at ground/power planes in isolation. Make sure there are no long, linear breaks due to closely spaced vias.
jonnew commented 8 years ago

closed in abeab1ace94b84919596763756aa7f3f7f7a8612