How do we make the 12V rail on the DIO board

[jvoigts]

The DIO board provides power to the external daughter boards via a 12V and a 5V rail.

The 5V rail can likely just come from some very high quality DC DC module, but the 12V rail deserves some thinking:

• do we need to add a separate 12V PCIe power connector like some GPUs have, or is our maximum current rating for daughter boards low enough for that not to matter? We're likely limited mostly by the gauge of the VHDCI cables, but i remember doing the math at TENSS and i think we can put a decent amperage trough these if needed.
• can we just take the 12V straight form the computer PSU? What standards can we expect? Maybe we should add a dedicated DC DC converter to clean it up a bit?
• What about over-current protection? Seems like we could add some protection here without any performance cost.

[jonnew]

These are additional concerns brought up by Andy Rose at UCL

• Something else you might want to consider is running a single 1v8 management power line instead of one of your 5V lines: That way you could power the EEPROM for access via I2C and gate the power to the 5V and 12V until compatibility has been verified from the EEPROM.
• I was also intrigued by the presence of the 5V power: Since your FPGA can only handle up to 3V3, you cannot use 5V signaling directly, and since you will need regulators to use the 12V at all, why not just run all the power lines at 12V, which would give you a lot more power available at the target end, given the 500mA per conductor limit on SCSI cables?

And some of my responses:

• 1v8 management rail: This is a good point. Also there are now parasitically power EEPROMS that don't even require a voltage rail to operate. They just take power of the DIO.

http://www.atmel.com/Images/Atmel-8903-SEEPROM-AT21CS01-Datasheet.pdf

• With respect to our choices for for a 5V rail, it was just a matter of convenience, e.g. for creating a 3.3V rail without the use of a DC-DC converter and without excessive power dissipation at the dropout regulator when stepping down from 12V. You are of course correct that we could get a lot more power out of the rails if we switched everything to 12 v rails.

8 * 0.5A * 12v = 48 Watts
vs
4 * 0.5A * 5v + 4 * 0.5A * 12A = 34 Watts

[jonnew]

With respect to overcurrent protection -- isn't that going to be built into whatever we are getting power from (ATX or motherboard?)

[jvoigts]

I do like the idea of gating the power lines until we verify the eeprom. We just know that someone somewhere will plug a nidaq breakout board in there and blow something up. If we can get by with a parasitically powered eeprom that would be sweet. That atmel looks good. Maybe that should also inform our choice of what to do with the i2c lines. Maybe we should also add switches to optionally turn this feature off and just turn the power on just for prototyping?

About the over-current protection - i think the computer power supply will happily melt the scsi cables if someone decides to hook up something big to the 12V rail - im not totally sure of the fuse setting on these but i think they can go to 16A. I once melted the insulation on one of these when testing out a brushless motor. The 5V rail is probably safer but we should double check the ATX spec.

[jonnew]

• Easiest way to gate power is probably to do it via the enable pins on the modules we put on the DIO board
• Overcurrent: yeah you're right. A lot of these modules come with settable overcurrent limit. Maybe we should just include that as something we want.
• The parasitically powered i2c chips will likely not work for us -- I suspect they are going to have a hell of a lot of trouble manipulating the capacitive load provided by a very long cable given their anemic characteristics. Could be wrong but that is something that should be pretty apparent on their data sheet.
• For power supply design/selection, LT provides this software: http://www.linear.com/designtools/software/#LTPower. I have not used it but LT's stuff is usually amazing so I bet this will be useful.

[jvoigts]

that all sounds good, also here's what we came up with last time we chatted:

• we could fairly easily set up a safe start-up protocol where we deliver a safe 5V rail (could even just be on one of the 4 5V pins?) until the EEPROM id is read. Then we both ramp up the available 5V current to max and turn on the 12V regulator.
• This would mean that we likely want either 4x 2A capable 12V supplies, one 8A one (500mA * 4 wires * 4 connectors). The first seems easier unless we can find somehting with 4 individually current limiting/fused outputs.
• Do we need a very high quality 12V rail? It feels like yes because thats where an analog front end would derive the reference rails etc. from, right?
• for the 5V rails, the same considerations mean that we'd likely want 4 individually current limiting supplies, or is it safe enough to split one across all 4 connectors?

[jonnew]

Low current startup and 5V rail consideration

• One issue with a low current start up: This does not prevent users from using the 5V rail for other things. This could overburden the current limit even for a valid breakout board. e.g. TTL dio board that uses the 5V as a rail for a bunch of (very inefficient :) converters. This causes voltage droop on the 5V line, EEPROM is not readable, system shuts down. WTF. Having a dedicated 1.8 or 3.3-EEPROM rail would get rid of this since the design spec would state that user was verboten from playing with this power rail other than for EEPROM.
• Above comment sort of speaks to last bullet point above. Take home is that the correct solution is to treat the 5V rails sorta like the 12V rails with relaxed noise requirements and have a separate 1.8V or 3.3V management rail.

Number of power modules

Definiately 4x 2A modules. That way power to each VHDCI connector is isolated all the way back to the ATX. In the case of catrostrophic failure, one module's over current limit would be tripped (or it would source 2A) and the the other breakouts would not even notice. Of couse, there should be some sour of signal back to the host that the current limit has been tripped so user can do something about it.

• Feature request uModule overcurrent indication should be sent to the host somehow. This might occupy 4 pins on the VHDCI connector.

Quality of 12V rail

Lets define high quality:

• Transient response: don't really need these guys to deal with huge current draw changes. This should be handled at the breakout board using a linear regulator / energy storage elements capable of dealing with fast large current draw changes (e.g. like cyclops has)
• Ripple: low, but not super low. Again, linear regulator at breakout board should take care of this as long as switching freq is in the 100's of KHz to very low MHz.
• High frequency residue: This is more of an issue. The LC characteristics of the long twisted pairs will help with this, but I've personally experienced huge reductions on noise on the intan chips when i switch the acquisition board's power supply away from a horrible wall wart to a bench top linear. Like 50%! The module should emit minimal high frequency switching content. Linear regulators are nearly transparent to this type of noise since it goes out into the 100's of MHz. For this reason, this information must be specified on the module's data sheet and eventually, we will need bench top testing with the near-field probe etc to make sure we can just safely ignore this frequency range at the breakout.
• Features:
  • [ ] Overcurrent protection / undervoltage lockout. Programable over-current limit would be amazing, because the EEPROM could store this info and this could be used to protect it from complete destruction in case of castostrophic user error (i.e. normal neuroscience use)
  • [ ] Overcurrent indication
  • [ ] Shutdown
  • [ ] Soft starte (maybe??)
  • [ ] ??