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open-ephys / rhythm

Intan Technologies Rhythm Verilog HDL code
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Display proper data on status LEDs #3

Open jvoigts opened 11 years ago

jvoigts commented 11 years ago

For now we're just displaying the raw data (subsampling bits for 16->8 bit) whenever the SPI is running:

.led1({SPI_running ? {led_a1_dat,led_a2_dat} : 16'b00000000 ,8'b00000000}), 
.led2({SPI_running ? {led_b1_dat,led_b2_dat} : 16'b00000000 ,8'b00000000}), 
.led3(24'b0), 
.led4(24'b0), 
.led5(24'b0), 
.led6(24'b0), 
.led7(24'b0), 
.led8(24'b0)

We should add displays for TTL and Analog in/out, as well as changing the headstage inputs to enable only when the software has recognized the headstage.