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open-logic
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open-logic
Open Logic HDL Standard Library
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Release/2.3.0
#74
obruendl
closed
5 days ago
1
Feature/doc
#73
obruendl
closed
6 days ago
1
Feature/cam
#72
obruendl
closed
6 days ago
1
Release 2.3.0
#71
obruendl
closed
5 days ago
0
Feature/firstbit only
#70
obruendl
closed
6 days ago
1
Feature/uart
#69
obruendl
closed
1 week ago
2
Question: Spurious "bit" in MISO line after first byte (SPI Slave)
#68
betocool-prog
closed
1 week ago
7
Feature/packet fifo
#67
obruendl
closed
2 weeks ago
1
DOC: Add sponsors button to readme
#66
obruendl
closed
3 weeks ago
0
DOC: Add FUNDING.yml
#65
obruendl
closed
3 weeks ago
0
adding the cdc or rdc checking
#64
neilwang0913
closed
6 days ago
4
fix spelling error
#63
Ravenwater
closed
3 weeks ago
0
Release 2.2.0
#62
obruendl
closed
1 month ago
1
DOC: Remove leftover comments from implementation
#61
obruendl
closed
1 month ago
0
Release 2.2.0
#60
obruendl
closed
1 month ago
1
Feature/cc handshake
#59
obruendl
closed
1 month ago
1
Feature/spi slave
#58
obruendl
closed
1 month ago
1
Feature/efinity tutorial scripts
#57
obruendl
closed
1 month ago
1
Feature/nvc workflow
#56
obruendl
closed
1 month ago
1
Enable Open Logic as an Orbit ip
#55
chaseruskin
opened
1 month ago
8
Minor fixes on documentation
#54
tasgomes
closed
1 month ago
1
Documentation: M_AXI_*Id omission signals clarification
#53
kuriousd
closed
1 month ago
1
Add Questasim Integration
#52
obruendl
closed
2 months ago
1
Feature/nvc
#51
obruendl
closed
2 months ago
1
AXI awid, bid, arid, rid signals missing in olo_axi_master_simple and olo_axi_master_full
#50
kuriousd
closed
1 month ago
3
Allow simulators other than GHDL and ModelSim in run.py
#49
nickg
closed
2 months ago
1
Releases/2.1.0
#48
obruendl
closed
2 months ago
1
Feature/efinix
#47
obruendl
closed
2 months ago
1
Feature/cache ghdl
#46
obruendl
closed
2 months ago
1
Feature/vunit junit report
#45
obruendl
closed
2 months ago
1
Feature/linting
#44
obruendl
opened
2 months ago
4
VSG Linting
#43
obruendl
opened
2 months ago
7
Feature/simtime optimization
#42
obruendl
closed
2 months ago
0
Signal 'M_Axi_RResp' is read in the process but is not in the sensitivity list
#41
kuriousd
closed
2 months ago
5
Feature/fusesoc
#40
obruendl
closed
2 months ago
0
Feature/spi master
#39
obruendl
closed
2 months ago
1
Release 2.0.0
#38
obruendl
closed
3 months ago
0
FEATURE: Add olo_base_flowctr_handler
#37
obruendl
closed
3 months ago
0
Feature/reset generator
#36
obruendl
closed
3 months ago
0
Implement Automatic Constraints for Quartus
#35
obruendl
closed
6 days ago
1
Make scoped constraints working for Verilog in Vivado
#34
obruendl
opened
3 months ago
0
Feature/quartus support
#33
obruendl
closed
3 months ago
0
Feature/verilog support
#32
obruendl
closed
3 months ago
0
Feature/doc fixes
#31
obruendl
closed
3 months ago
0
Add support for System Verilog
#30
obruendl
closed
3 months ago
2
Figures not well readable in Dark Mode
#29
obruendl
closed
3 months ago
2
Release/1.2.0
#28
obruendl
closed
3 months ago
0
Feature/debounce
#27
obruendl
closed
3 months ago
0
Feature/clk meas
#26
obruendl
closed
3 months ago
0
Release 1.1.0
#25
obruendl
closed
3 months ago
0
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