Closed Grubby0624 closed 2 years ago
I believe this is just an architectural limit in the processor memory logic. Maybe @esteban012 or @stermole can comment more.
Yes, it's an architectural limit of the logic. You are correct that the ratio is DIMM freq / nest freq and 1.5 is the upper limit of that ratio.
Ok, I see. Thank you so much
https://github.com/open-power/hostboot/blob/cb943f25a60c6a4b0409c95b7da12e409e648ab9/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/freq_workarounds.C#L61 Excuse me, how is this ratio determined, and is this the upper limit of nest freq and DIMM freq, so if the nest freq of P9 is 1866MHz, the maximum frequency of DIMM can only reach 2666MHz?