dcrowell77
commented
1 year ago The SMP fabric that connects POWER processors is organized into groups of chips and members of those groups. Every chip in the fabric must have a unique position in the fabric, called the Topology Id in P10. Groups are logical constructs based on both physical wiring and choices made about system performance. Depending on the wiring on the SMP bus you can often choose a variety of configurations, each with pros/cons. In some cases the physical wiring forces you to choose a specific configuration. Traditionally, the group portion of the fabric id has been equated with a physical node/drawer. For example in our P10 high-end system we have 4 chips on each drawer that are all in the same group. For all of the P10 eBMC systems, we run in "chip is group" mode which just means that every processor chip acts as its own group of 1.
I'm grossly simplifying a very complex set of trade-offs, but at a high-level the groups define how many "hops" it takes to get from one place to another. For example, if we're in GGCC mode with 2 groups and proc-0 (GG=0, CC=0) wants to read memory behind proc-5 (GG=1,CC=1), how does it get there? The hardware will route the request first to proc-4 (GG=1,CC=0), then to proc-5. So it hops between groups, then between chips in that group (i might have that backwards but details not important).
https://github.com/open-power/hostboot/blob/d775c5366ded869215d5ee126fc474f64e6e00da/src/import/chips/p10/procedures/xml/attribute_info/p10_nest_attributes.xml#L126 Hello, I have a question to ask: ATTR here PROC FABRIC TOPOLOGY What are the physical meanings of the Group ID and Chip ID of Proc marked with ID? What is the difference between Procs under the same group and Procs under different groups?