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CAPI SNAP Framework Hardware and Software
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Error building v0.6.1 tag with Vivado 2016.4 #114

Closed KennethWilke closed 7 years ago

KennethWilke commented 7 years ago

Howdy,

I'm trying to build the memcpy example for the KU3 with Vivado 2016.4, and am running into errors during the synthesis of 'psl_fpga'. Below is the results of my make attempt

$ make config image
-e  [COPY] psl build env
-e  [CONFIG] setup psl_fpga.tcl
directory /home/kwilke/workprojects/pslse exists
directory /home/kwilke/workprojects/donut/software exists
directory /home/kwilke/workprojects/donut/hardware exists
compile pslse args=  pwd=/home/kwilke/workprojects/pslse subdir=afu_driver/src RC=0 error lines=0
compile pslse args=  pwd=/home/kwilke/workprojects/pslse subdir=pslse RC=0 error lines=0
compile pslse args=  pwd=/home/kwilke/workprojects/pslse subdir=libcxl RC=0 error lines=0
compile pslse args=  pwd=/home/kwilke/workprojects/pslse subdir=debug RC=0 error lines=0
compile sw args=  pwd=/home/kwilke/workprojects/donut/software subdir=. RC=0 error lines=0
run Vivado setup scripts
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub

****** Vivado v2016.4 (64-bit)
  **** SW Build 1733598 on Wed Dec 14 22:35:42 MST 2016
  **** IP Build 1731160 on Wed Dec 14 23:47:21 MST 2016
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source create_ip.tcl
# set root_dir     $::env(DONUT_HARDWARE_ROOT)
# set fpga_part    $::env(FPGACHIP)
# set dimm_dir     $::env(DIMMTEST)
# set ip_dir       $root_dir/ip
# set ddr3_used    $::env(DDR3_USED)
# set bram_used    $::env(BRAM_USED)
# set axi_id_width $::env(NUM_OF_ACTIONS)
# exec rm -rf $ip_dir
# create_project managed_ip_project $ip_dir/managed_ip_project -part $fpga_part -ip
# set_property target_language VHDL [current_project]
# set_property target_simulator IES [current_project]
# create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.3 -module_name ram_520x64_2p -dir $ip_dir
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2016.4/data/ip'.
INFO: [Device 21-403] Loading part xcku060-ffva1156-2-e
create_ip: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1571.211 ; gain = 570.219 ; free physical = 3221 ; free virtual = 27791
# set_property -dict [list CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {520} CONFIG.Write_Depth_A {64} CONFIG.Operating_Mode_A {NO_CHANGE} CONFIG.Enable_A {Always_Enabled} CONFIG.Write_Width_B {520} CONFIG.Enable_B {Always_Enabled} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Read_Width_A {520} CONFIG.Read_Width_B {520} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Register_PortB_Output_of_Memory_Primitives {true} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips ram_520x64_2p]
# generate_target {instantiation_template} [get_files $ip_dir/ram_520x64_2p/ram_520x64_2p.xci]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'ram_520x64_2p'...
# generate_target all [get_files  $ip_dir/ram_520x64_2p/ram_520x64_2p.xci]
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'ram_520x64_2p'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'ram_520x64_2p'...
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'ram_520x64_2p'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'ram_520x64_2p'...
# export_ip_user_files -of_objects [get_files $ip_dir/ram_520x64_2p/ram_520x64_2p.xci] -no_script -force -quiet
# create_ip_run [get_files -of_objects [get_fileset sources_1] $ip_dir/ram_520x64_2p/ram_520x64_2p.xci]
# launch_run -jobs 2 ram_520x64_2p_synth_1
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub
[Wed Jan 18 10:09:23 2017] Launched ram_520x64_2p_synth_1...
Run output will be captured here: /home/kwilke/workprojects/donut/hardware/ip/managed_ip_project/managed_ip_project.runs/ram_520x64_2p_synth_1/runme.log
# export_simulation -of_objects [get_files $ip_dir/ram_520x64_2p/ram_520x64_2p.xci] -directory $ip_dir/ip_user_files/sim_scripts -force -quiet
# create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.3 -module_name ram_584x64_2p -dir $ip_dir
# set_property -dict [list CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {584} CONFIG.Write_Depth_A {64} CONFIG.Operating_Mode_A {NO_CHANGE} CONFIG.Enable_A {Always_Enabled} CONFIG.Write_Width_B {584} CONFIG.Enable_B {Always_Enabled} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Read_Width_A {584} CONFIG.Read_Width_B {584} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Register_PortB_Output_of_Memory_Primitives {true} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips ram_584x64_2p]
# generate_target {instantiation_template} [get_files $ip_dir/ram_584x64_2p/ram_584x64_2p.xci]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'ram_584x64_2p'...
# generate_target all [get_files  $ip_dir/ram_584x64_2p/ram_584x64_2p.xci]
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'ram_584x64_2p'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'ram_584x64_2p'...
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'ram_584x64_2p'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'ram_584x64_2p'...
# export_ip_user_files -of_objects [get_files $ip_dir/ram_584x64_2p/ram_584x64_2p.xci] -no_script -force -quiet
# create_ip_run [get_files -of_objects [get_fileset sources_1] $ip_dir//ram_584x64_2p/ram_584x64_2p.xci]
# launch_run -jobs 2 ram_584x64_2p_synth_1
[Wed Jan 18 10:09:25 2017] Launched ram_584x64_2p_synth_1...
Run output will be captured here: /home/kwilke/workprojects/donut/hardware/ip/managed_ip_project/managed_ip_project.runs/ram_584x64_2p_synth_1/runme.log
# export_simulation -of_objects [get_files $ip_dir/ram_584x64_2p/ram_584x64_2p.xci] -directory $ip_dir/ip_user_files/sim_scripts -force -quiet
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub
# create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.* -module_name fifo_513x512 -dir $ip_dir
# set_property -dict [list CONFIG.INTERFACE_TYPE {Native} CONFIG.Input_Data_Width {513} CONFIG.Input_Depth {512} CONFIG.Valid_Flag {false} CONFIG.Performance_Options {First_Word_Fall_Through} CONFIG.Write_Acknowledge_Flag {false} CONFIG.Programmable_Full_Type {Single_Programmable_Full_Threshold_Constant} CONFIG.Full_Threshold_Assert_Value {490} CONFIG.Output_Data_Width {513} CONFIG.Output_Depth {512} CONFIG.Reset_Type {Synchronous_Reset} CONFIG.Data_Count_Width {9} CONFIG.Write_Data_Count_Width {9} CONFIG.Read_Data_Count_Width {9} CONFIG.Full_Threshold_Negate_Value {489} CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} CONFIG.Full_Threshold_Assert_Value_wach {15} CONFIG.Empty_Threshold_Assert_Value_wach {14} CONFIG.FIFO_Implementation_wdch {Common_Clock_Block_RAM} CONFIG.Input_Depth_wdch {1024} CONFIG.Full_Threshold_Assert_Value_wdch {511} CONFIG.Empty_Threshold_Assert_Value_wdch {510} CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} CONFIG.Full_Threshold_Assert_Value_wrch {15} CONFIG.Empty_Threshold_Assert_Value_wrch {14} CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} CONFIG.Full_Threshold_Assert_Value_rach {15} CONFIG.Empty_Threshold_Assert_Value_rach {14} CONFIG.FIFO_Implementation_rdch {Common_Clock_Block_RAM} CONFIG.Input_Depth_rdch {1024} CONFIG.Full_Threshold_Assert_Value_rdch {511} CONFIG.Empty_Threshold_Assert_Value_rdch {510} CONFIG.FIFO_Implementation_axis {Common_Clock_Block_RAM} CONFIG.Input_Depth_axis {1024} CONFIG.Full_Threshold_Assert_Value_axis {511} CONFIG.Empty_Threshold_Assert_Value_axis {510}] [get_ips fifo_513x512]
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Empty_Threshold_Assert_Value_wrch' from '1022' to '14' has been ignored for IP 'fifo_513x512'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Empty_Threshold_Assert_Value_wdch' from '1022' to '510' has been ignored for IP 'fifo_513x512'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Empty_Threshold_Assert_Value_wach' from '1022' to '14' has been ignored for IP 'fifo_513x512'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Empty_Threshold_Assert_Value_rdch' from '1022' to '510' has been ignored for IP 'fifo_513x512'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Empty_Threshold_Assert_Value_rach' from '1022' to '14' has been ignored for IP 'fifo_513x512'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Empty_Threshold_Assert_Value_axis' from '1022' to '510' has been ignored for IP 'fifo_513x512'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Full_Threshold_Assert_Value_wrch' from '1023' to '15' has been ignored for IP 'fifo_513x512'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Full_Threshold_Assert_Value_wdch' from '1023' to '511' has been ignored for IP 'fifo_513x512'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Full_Threshold_Assert_Value_wach' from '1023' to '15' has been ignored for IP 'fifo_513x512'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Full_Threshold_Assert_Value_rdch' from '1023' to '511' has been ignored for IP 'fifo_513x512'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Full_Threshold_Assert_Value_rach' from '1023' to '15' has been ignored for IP 'fifo_513x512'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Full_Threshold_Assert_Value_axis' from '1023' to '511' has been ignored for IP 'fifo_513x512'
# generate_target {instantiation_template} [get_files $ip_dir/fifo_513x512/fifo_513x512.xci]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'fifo_513x512'...
# generate_target all [get_files  $ip_dir/fifo_513x512/fifo_513x512.xci]
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_513x512'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fifo_513x512'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'fifo_513x512'...
# export_ip_user_files -of_objects [get_files $ip_dir/fifo_513x512/fifo_513x512.xci] -no_script -force -quiet
# create_ip_run [get_files -of_objects [get_fileset sources_1] $ip_dir/fifo_513x512/fifo_513x512.xci]
# launch_run -jobs 1 fifo_513x512_synth_1
[Wed Jan 18 10:09:27 2017] Launched fifo_513x512_synth_1...
Run output will be captured here: /home/kwilke/workprojects/donut/hardware/ip/managed_ip_project/managed_ip_project.runs/fifo_513x512_synth_1/runme.log
# export_simulation -of_objects [get_files $ip_dir/fifo_513x512/fifo_513x512.xci] -directory $ip_dir/ip_user_files/sim_scripts -force -quiet
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub
# if { $ddr3_used == TRUE } {
#   #create clock converter for axi_card_mem
#   create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name axi_clock_converter -dir $ip_dir
#   set_property -dict [list CONFIG.ADDR_WIDTH {33} CONFIG.DATA_WIDTH {512} CONFIG.ID_WIDTH $axi_id_width] [get_ips axi_clock_converter]
#   generate_target {instantiation_template} [get_files $ip_dir/axi_clock_converter/axi_clock_converter.xci]
#   generate_target all [get_files  $ip_dir/axi_clock_converter/axi_clock_converter.xci]
#   export_ip_user_files -of_objects [get_files $ip_dir/axi_clock_converter/axi_clock_converter.xci] -no_script -force -quiet
#   create_ip_run [get_files -of_objects [get_fileset sources_1] $ip_dir/axi_clock_converter/axi_clock_converter.xci]
#   launch_run -jobs 1 axi_clock_converter_synth_1
#   export_simulation -of_objects [get_files $ip_dir/axi_clock_converter/axi_clock_converter.xci] -directory $ip_dir/ip_user_files/sim_scripts -force -quiet
# 
#   if { $bram_used == TRUE } {
#     #create BlockRAM
#     create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.3 -module_name block_RAM -dir  $ip_dir
#     set_property -dict [list CONFIG.Interface_Type {AXI4} CONFIG.Write_Width_A {128} CONFIG.AXI_ID_Width $axi_id_width CONFIG.Write_Depth_A {32768} CONFIG.Use_AXI_ID {true} CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Read_Width_A {128} CONFIG.Operating_Mode_A {READ_FIRST} CONFIG.Write_Width_B {128} CONFIG.Read_Width_B {128} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Enable_B {Use_ENB_Pin} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Use_RSTB_Pin {true} CONFIG.Reset_Type {ASYNC} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips block_RAM]
#     generate_target {instantiation_template} [get_files $ip_dir/block_RAM/block_RAM.xci]
#     set_property generate_synth_checkpoint false [get_files $ip_dir/block_RAM/block_RAM.xci]
#     generate_target all [get_files $ip_dir/block_RAM/block_RAM.xci]
#     export_ip_user_files -of_objects [get_files $ip_dir/block_RAM/block_RAM.xci] -no_script -force -quiet
#     export_simulation -of_objects [get_files $ip_dir/block_RAM/block_RAM.xci] -directory $ip_dir/ip_user_files/sim_scripts -force -quiet
#   } else {
#     #DDR3 create ddr3sdramm with ECC
#     create_ip -name ddr3 -vendor xilinx.com -library ip -version 1.* -module_name ddr3sdram -dir $ip_dir
#     set_property -dict [list CONFIG.C0.DDR3_TimePeriod {1250} CONFIG.C0.DDR3_InputClockPeriod {2500} CONFIG.C0.DDR3_MemoryType {SODIMMs} CONFIG.C0.DDR3_MemoryPart {CUSTOM_MT18KSF1G72HZ-1G6} CONFIG.C0.DDR3_AxiSelection {true} CONFIG.C0.DDR3_AxiDataWidth {512} CONFIG.C0.DDR3_CustomParts $dimm_dir/example/dimm_test-admpcieku3-v3_0_0/fpga/ip-2015.3/custom_parts.csv CONFIG.C0.DDR3_isCustom {true} CONFIG.Simulation_Mode {Unisim} CONFIG.Internal_Vref {false} CONFIG.C0.DDR3_DataWidth {72} CONFIG.C0.DDR3_DataMask {false} CONFIG.C0.DDR3_Ecc {true} CONFIG.C0.DDR3_CasLatency {11} CONFIG.C0.DDR3_CasWriteLatency {8} CONFIG.C0.DDR3_AxiAddressWidth {33} CONFIG.C0.DDR3_AxiIDWidth $axi_id_width] [get_ips ddr3sdram]
#     generate_target {instantiation_template} [get_files $ip_dir/ddr3sdram/ddr3sdram.xci]
#     generate_target all [get_files  $ip_dir/ddr3sdram/ddr3sdram.xci]
#     export_ip_user_files -of_objects [get_files $ip_dir/ddr3sdram/ddr3sdram.xci] -no_script -force -quiet
#     create_ip_run [get_files -of_objects [get_fileset sources_1] $ip_dir/ddr3sdram/ddr3sdram.xci]
#     launch_run -jobs 10 ddr3sdram_synth_1
#     export_simulation -of_objects [get_files $ip_dir/ddr3sdram/ddr3sdram.xci] -directory $ip_dir/ip_user_files/sim_scripts -force -quiet
#   }
# }
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_clock_converter'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_clock_converter'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_clock_converter'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'axi_clock_converter'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'axi_clock_converter'...
[Wed Jan 18 10:09:28 2017] Launched axi_clock_converter_synth_1...
Run output will be captured here: /home/kwilke/workprojects/donut/hardware/ip/managed_ip_project/managed_ip_project.runs/axi_clock_converter_synth_1/runme.log
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub
create_ip: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1661.434 ; gain = 27.328 ; free physical = 2704 ; free virtual = 27420
INFO: [IP_Flow 19-3484] Absolute path of file '/home/kwilke/workprojects/ad-ku3/dimm_test-admpcieku3-v3_0_0/example/dimm_test-admpcieku3-v3_0_0/fpga/ip-2015.3/custom_parts.csv' provided. It will be converted relative to IP Instance files '../../../../ad-ku3/dimm_test-admpcieku3-v3_0_0/example/dimm_test-admpcieku3-v3_0_0/fpga/ip-2015.3/custom_parts.csv'
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'ddr3sdram'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'ddr3sdram'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'ddr3sdram'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'ddr3sdram'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'ddr3sdram'...
Exporting to file /home/kwilke/workprojects/donut/hardware/ip/ddr3sdram/bd_0/hw_handoff/ddr3sdram_microblaze_mcs.hwh
Generated Block Design Tcl file /home/kwilke/workprojects/donut/hardware/ip/ddr3sdram/bd_0/hw_handoff/ddr3sdram_microblaze_mcs_bd.tcl
Generated Hardware Definition File /home/kwilke/workprojects/donut/hardware/ip/ddr3sdram/bd_0/hdl/ddr3sdram_microblaze_mcs.hwdef
generate_target: Time (s): cpu = 00:00:22 ; elapsed = 00:00:36 . Memory (MB): peak = 1790.703 ; gain = 66.953 ; free physical = 343 ; free virtual = 25164
[Wed Jan 18 10:10:28 2017] Launched ddr3sdram_synth_1...
Run output will be captured here: /home/kwilke/workprojects/donut/hardware/ip/managed_ip_project/managed_ip_project.runs/ddr3sdram_synth_1/runme.log
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub
# close_project
INFO: [Common 17-206] Exiting Vivado at Wed Jan 18 10:10:37 2017...
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub

****** Vivado v2016.4 (64-bit)
  **** SW Build 1733598 on Wed Dec 14 22:35:42 MST 2016
  **** IP Build 1731160 on Wed Dec 14 23:47:21 MST 2016
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source create_framework.tcl
# set xilinx_vivado $::env(XILINX_VIVADO)
# set root_dir    $::env(DONUT_HARDWARE_ROOT)
# set fpga_part   $::env(FPGACHIP)
# set pslse_dir   $::env(PSLSE_ROOT)
# set dimm_dir    $::env(DIMMTEST)
no such variable
    (read trace on "::env(IES_LIBS)")
    invoked from within
"set ies_libs    $::env(IES_LIBS)"
    (file "create_framework.tcl" line 24)
INFO: [Common 17-206] Exiting Vivado at Wed Jan 18 10:11:03 2017...
error in create_framework
sed: can't read /home/kwilke/workprojects/donut/hardware/sim/xsim/top.sh: No such file or directory
sed: can't read /home/kwilke/workprojects/donut/hardware/sim/xsim/top.sh: No such file or directory
-e  [CREATE_ENVIRONMENT] done (Wed Jan 18 10:09:04 CST 2017)
-e  [CREATE] /home/kwilke/workprojects/donut/hardware/build/Sources/prj/afu.prj
grep: /home/kwilke/workprojects/donut/hardware/sim/xsim/file_info.txt: No such file or directory
cut: /home/kwilke/workprojects/donut/hardware/sim/xsim/file_info.txt: No such file or directory
-e  [CREATE] /home/kwilke/workprojects/donut/hardware/build/Sources/prj/psl_fpga.prj
PATCH .tcl FILES
PATCH .vhd FILES
PATCH .vhd FILES for DDR3 usage
patching file ./Sources/top/psl_fpga.vhdl
PATCH build date
basename: missing operand
Try 'basename --help' for more information.
-e  [CONFIG] done (Wed Jan 18 10:11:04 CST 2017)
-e  [BUILD IMAGE] start (Wed Jan 18 10:11:04 CST 2017)
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub

****** Vivado v2016.4 (64-bit)
  **** SW Build 1733598 on Wed Dec 14 22:35:42 MST 2016
  **** IP Build 1731160 on Wed Dec 14 23:47:21 MST 2016
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source psl_fpga.tcl -notrace
Critical Warning: Specified script version 2014.3 does not match Vivado version 2016.4.
Either change the version of scripts being used or run with the correct version of Vivado.
#HD: Running synthesis for block psl_fpga
    Writing results to: ./Synth/psl_fpga
#HD: Setting Tcl Params:
    hd.visual == 1
    Parsing PRJ file: ./Sources/prj/psl_fpga.prj
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2016.4/data/ip'.
WARNING: [IP_Flow 19-2162] IP 'action_axi_register_slice_0_0' is locked:
* IP definition 'AXI Register Slice (2.1)' for IP 'action_axi_register_slice_0_0' (customized with software release 2015.4) has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'action_axi_interconnect_0_0' is locked:
* Newer version is available in the IP Catalog.
* IP definition 'AXI Interconnect (2.1)' for IP 'action_axi_interconnect_0_0' (customized with software release 2015.4) has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
    Generating output for IP action_axi_interconnect_0_0
WARNING: [IP_Flow 19-2162] IP 'action_axi_interconnect_1_0' is locked:
* Newer version is available in the IP Catalog.
* IP definition 'AXI Interconnect (2.1)' for IP 'action_axi_interconnect_1_0' (customized with software release 2015.4) has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
    Generating output for IP action_axi_interconnect_1_0
WARNING: [IP_Flow 19-2162] IP 'action_action_memcopy_0_0' is locked:
* IP definition 'action_memcopy (1.0)' for IP 'action_action_memcopy_0_0' (customized with software release 2015.4) was not found in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'action_axi_interconnect_2_0' is locked:
* Newer version is available in the IP Catalog.
* IP definition 'AXI Interconnect (2.1)' for IP 'action_axi_interconnect_2_0' (customized with software release 2015.4) has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
    Generating output for IP action_axi_interconnect_2_0
WARNING: [IP_Flow 19-3664] IP 'ram_520x64_2p' generated file not found '/home/kwilke/workprojects/donut/hardware/ip/ram_520x64_2p/ram_520x64_2p.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ram_520x64_2p' generated file not found '/home/kwilke/workprojects/donut/hardware/ip/ram_520x64_2p/ram_520x64_2p_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ram_520x64_2p' generated file not found '/home/kwilke/workprojects/donut/hardware/ip/ram_520x64_2p/ram_520x64_2p_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ram_520x64_2p' generated file not found '/home/kwilke/workprojects/donut/hardware/ip/ram_520x64_2p/ram_520x64_2p_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ram_520x64_2p' generated file not found '/home/kwilke/workprojects/donut/hardware/ip/ram_520x64_2p/ram_520x64_2p_sim_netlist.vhdl'. Please regenerate to continue.
    Synthesizing IP ram_520x64_2p
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub
ERROR: [Common 17-176] Overwrite of existing file isn't enabled.  Please specify -force to overwrite file  [/home/kwilke/workprojects/donut/hardware/ip/ram_520x64_2p/ram_520x64_2p.dcp]
WARNING: [IP_Flow 19-3664] IP 'ddr3sdram' generated file not found '/home/kwilke/workprojects/donut/hardware/ip/ddr3sdram/ddr3sdram.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ddr3sdram' generated file not found '/home/kwilke/workprojects/donut/hardware/ip/ddr3sdram/ddr3sdram_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ddr3sdram' generated file not found '/home/kwilke/workprojects/donut/hardware/ip/ddr3sdram/ddr3sdram_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ddr3sdram' generated file not found '/home/kwilke/workprojects/donut/hardware/ip/ddr3sdram/ddr3sdram_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ddr3sdram' generated file not found '/home/kwilke/workprojects/donut/hardware/ip/ddr3sdram/ddr3sdram_sim_netlist.vhdl'. Please regenerate to continue.
    Synthesizing IP ddr3sdram
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub
    Adding XDC files
    Running synth_design
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'refclk200_p' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'refclk200_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_sys_clk_p' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_sys_clk_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_ddr3_addr' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_ddr3_ba' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_ddr3_ras_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_ddr3_cas_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_ddr3_reset_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_ddr3_cs_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_ddr3_cke' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_ddr3_ck_p' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_ddr3_ck_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_ddr3_we_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_ddr3_dm' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_ddr3_dq' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_ddr3_dqs_p' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_ddr3_dqs_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c0_ddr3_odt' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_sys_clk_p' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_sys_clk_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_ddr3_addr' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_ddr3_ba' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_ddr3_ras_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_ddr3_cas_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_ddr3_reset_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_ddr3_cs_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_ddr3_cke' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_ddr3_ck_p' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_ddr3_ck_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_ddr3_we_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_ddr3_dm' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_ddr3_dq' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_ddr3_dqs_p' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_ddr3_dqs_n' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-3493] module 'psl_accel' declared at '/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_accel.vhdl:11' does not have matching formal port for component port 'c1_ddr3_odt' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:408]
ERROR: [Synth 8-285] failed synthesizing module 'psl_fpga' [/home/kwilke/workprojects/donut/hardware/build/Sources/top/psl_fpga.vhdl:114]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

ERROR: synth_design command "synth_design -mode default -flatten_hierarchy none -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5 -no_iobuf -top psl_fpga -part xcku060-ffva1156-2-e" failed.
See log file ./Synth/psl_fpga/psl_fpga_synth_design.rds for more details.
    while executing
"error $errMsg"
    (procedure "command" line 66)
    invoked from within
"command "synth_design -mode default $options -top $moduleName -part $part" "$resultDir/${moduleName}_synth_design.rds""
    invoked from within
"if {$topLevel} {
      command "synth_design -mode default $options -top $moduleName -part $part" "$resultDir/${moduleName}_synth_design.rds"
   } els..."
    (procedure "synth" line 1)
    invoked from within
"synth $module"
    ("foreach" body line 3)
    invoked from within
"foreach module $modules {
      if {[get_attribute module $module synth]} {
       synth $module
    }
  }"
    invoked from within
"if {[llength $modules] > 0} {
   foreach module $modules {
      if {[get_attribute module $module synth]} {
       synth $module
    }
  }
}"
    (file "./Tcl/run.tcl" line 19)

    while executing
"source $tclDir/run.tcl"
    (file "psl_fpga.tcl" line 147)
INFO: [Common 17-206] Exiting Vivado at Wed Jan 18 10:24:39 2017...
Makefile:92: recipe for target 'image' failed
make: *** [image] Error 1
jsvogt commented 7 years ago

Does it work now?

KennethWilke commented 7 years ago

I've switched to use the v0.7.1 tag and my builds are proceeding now without error, going to close this issue out.