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open-power / snap

CAPI SNAP Framework Hardware and Software
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XSim simulation fails with ddr3 sdram model #85

Closed boekholt closed 7 years ago

boekholt commented 7 years ago

Simulation with ddr3 sdram model (based on the patched dimmtest model) fails with the error message:

ERROR: File: /afs/vlsilab.boeblingen.ibm.com/proj/fpga/framework/cards/dimm_test-admpcieku3-v3_0_0_xsim/fpga/lib/ddr3_sdram_model-v1_1_0/src/ddr3_sdram_data_sv.sv Line: 280 Accessing non-static members of a null object is not allowed.

joergkayser commented 7 years ago

this was once working with Vivado 2015.4. The error msg is unknown to me and needs more investigation. The patches in dimm_test*xsim are necessary to bypass the 2**31 error.

boekholt commented 7 years ago

I did open this issue because the problem did occur with Vivado 2015.4 and DIMMTEST=dimm_test*xsim.

joergkayser commented 7 years ago

I tested donut master (acc94ac 2017-01-11) with DDR3_USED=TRUE, ACTION_ROOT=.../action_examples/memcopy, DIMMTEST=.../cards/dimm_test-admpcieku3-v3_0_0_xsim, Simulator=xsim Results: make clean config model ran fine run_sim -app tools/stage2 -a2 -vvv -z1 -t100 ran fine as well Please recreate

boekholt commented 7 years ago

run_sim -app tools/stage2 -a2 -vvv -z1 -t100 is a host -> host test. That also passes for me. I am getting the error message as posted in my first comment for the following stage2 tests: -a3, -a5, -a6. All those are accessing the on-card DRAM.

jsvogt commented 7 years ago

Wait for Vivado 2017.1 to try again. From Lisa : The early access of the 2017.1 release is March 15, 2017. The customer access time is expected to be April 15, 2017.

jsvogt commented 7 years ago

Does not occur with the Xilinx DDR3 simulation model from the example design.

jsvogt commented 7 years ago

Re-test with Vivado 2017.1 needed, or close due to change to Xilinx MIG memory model?

joergkayser commented 7 years ago

we changed to the Xilinx memory model and the error is gone