search

open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
GNU Affero General Public License v3.0
701 stars 237 forks source link

焦博士你好，我想问一下关于openofdm_tx模块的dot11_tx.v中，关于BCC模块的reset机制问题。 #105

Closed wjq110 closed 3 months ago

wjq110 commented 8 months ago

assign enc_reset = phy_tx_arest | state1 == S1_WAIT_PKT | plcp_bit_cnt == 23 | plcp_bit_cnt == 47; 您原来的代码中，会在SIG字段的第23bit和第47bit对BCC模块进行reset。当发送ht帧时，这个机制会导致在SIG字段中重置BCC模块，与接收机的解码机制是不是有一定区别。接收机中好像时直接把所有数据直接一起解码的，不会区分不同symbol。

ll550 commented 1 month ago

I guess because the encoded bits sequence in the rx side appended the tail bits for each field that will revert the decoder back to the initial state. so the decoder can accept the complete sequence.