the synthesis (Run synthesis) stage fails.

open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

GNU Affero General Public License v3.0

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Closed chenmo234 closed 3 months ago

chenmo234 commented 4 months ago

20240529142007 https://github.com/open-sdr/openwifi-hw/issues/59 My steps are exactly the same as his, and I have already added the Viterbi Decoder.

AnVuNam commented 3 months ago

Hi, I'm also having the same problem. Have you solved it yet?

chenmo234 commented 3 months ago

Hi, I'm also having the same problem. Have you solved it yet?

Yes, this is my contact information. c2385405729