the synthesis (Run synthesis) stage fails.

open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

GNU Affero General Public License v3.0

701 stars 237 forks source link

Closed chenmo234 closed 5 months ago

chenmo234 commented 5 months ago

20240529142007 https://github.com/open-sdr/openwifi-hw/issues/59 My steps are exactly the same as his, and I have already added the Viterbi Decoder.

AnVuNam commented 5 months ago

Hi, I'm also having the same problem. Have you solved it yet?

chenmo234 commented 5 months ago

Hi, I'm also having the same problem. Have you solved it yet?

Yes, this is my contact information. c2385405729