Simulation of openofdm_rx

[hyanki]

Hi Its really great. I want to know that how can i simulate these designs? Regards hyanki

[JiaoXianjun]

Yes it can be simulated. I simulated it in Vivado via the testbench: https://github.com/open-sdr/openofdm/blob/abbe9ecde9e08267386fd7263707c9a9557df4c3/verilog/dot11_tb.v

To carry out simulation, you need to do it in directory openwifi/openwifi-hw/ip/openofdm_rx instead of only clone openofdm project.

Before simulation, you need to create a vivado project via openofdm_rx.tcl.

All these steps you can find in openwifi and openwifi-hw README.

[hyanki]

Hi Jiao Xianjun thanks for your response. Is it possible to simulate icarus verilog?

Regards hyanki

[JiaoXianjun]

I think it is possible.

[hyanki]

Hi Jiao Xianjun Do you have any idea how it can be done because i have not worked on icarus. Regards hyanki

[JiaoXianjun]

I also do not have experience on that tool. But I guess the procedure should be similar. Add all source files into the project then simulate the top level test bench.

[hyanki]

I have tried but it gives error that modules are missing. any way in vivado how you have feeded input data to rf modulde and how you have set register setting i mean min_plateu etc.

[mmehari]

Hello, The original openofdm module supports icarus verilog simulation and you can use the following commit (https://github.com/jhshi/openofdm/tree/2f0e0ba95385affa426dc11eba6effab37b8778b) for your test.

This, however, does not include our development but if you need that, you have to use vivado simulation as @JiaoXianjun pointed you.

[hyanki]

Hi michael When compile list of files by below command iverilog -v -c dot11_modules.list -o dot11.out It generates dot11.out file. After that how can i run dot11_tb.v file to get dot11.vcd file. I am searching how to use make file to run for everything. Right now i don't have vivado so i have to use icarus. Please help me. Regards Hyanki

On Wed, 10 Jun 2020, 16:40 Michael Mehari, notifications@github.com wrote:

Hello, The original openofdm module supports icarus verilog simulation and you can use the following commit ( https://github.com/jhshi/openofdm/tree/2f0e0ba95385affa426dc11eba6effab37b8778b) for your test.

This, however, does not include our development but if you need that, you have to use vivado simulation as @JiaoXianjun https://github.com/JiaoXianjun pointed you.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/open-sdr/openwifi-hw/issues/11#issuecomment-641931762, or unsubscribe https://github.com/notifications/unsubscribe-auth/AC2RBWOEB3R2P72X672AV5DRV5S3XANCNFSM4NZDSYNA .

[mmehari]

How did you compile your program There is already a Makefile available and if you type make -n it will show you

iverilog -v -c dot11_modules.list -o dot11.out -DDEBUG_PRINT dot11_tb.v
vvp -v -n dot11.out

Which means you are missing the second command and that will generate the dot11.vcd file.

[hyanki]

Hi mmehari it is working now Thanks a lot. regards hyanki

[hyanki]

Hi problem is resolved now thanks a lot